scholarly journals [Paper] Digital Calibration for a 2-Stage Cyclic Analog-to-Digital Converter Used in a 33-Mpixel 120-fps SHV CMOS Image Sensor

2014 ◽  
Vol 2 (2) ◽  
pp. 102-107 ◽  
Author(s):  
Toshihisa Watabe ◽  
Kazuya Kitamura ◽  
Tetsuya Hayashida ◽  
Tomohiko Kosugi ◽  
Hiroshi Ohtake ◽  
...  
Keyword(s):  
Cmos Image Sensor ◽  
Image Sensor ◽  
Digital Calibration ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Cyclic Analog

A 33-Megapixel 120-Frames-Per-Second 2.5-Watt CMOS Image Sensor With Column-Parallel Two-Stage Cyclic Analog-to-Digital Converters

2012 ◽  
Vol 59 (12) ◽  
pp. 3426-3433 ◽  
Author(s):  
Kazuya Kitamura ◽  
Toshihisa Watabe ◽  
Takehide Sawamoto ◽  
Tomohiko Kosugi ◽  
Tomoyuki Akahori ◽  
...  
Keyword(s):  
Cmos Image Sensor ◽  
Image Sensor ◽  
Analog To Digital Converters ◽  
Two Stage ◽  
Analog To Digital ◽  
Cyclic Analog

scholarly journals A 12-bit 30 MS/s Successive Approximation-Register Analog-to-Digital Converter with Foreground Digital Calibration Algorithm

Symmetry ◽  
2020 ◽  
Vol 12 (1) ◽  
pp. 165
Author(s):  
Shouping Li ◽  
Yang Guo ◽  
Jianjun Chen ◽  
Bin Liang
Keyword(s):  
Successive Approximation ◽  
High Speed ◽  
Low Noise ◽  
Digital Calibration ◽  
Cmos Process ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Dynamic Comparator ◽  
Analog To Digital ◽  
Calibration Algorithm

This paper presents a foreground digital calibration algorithm based on a dynamic comparator that aims to reduce comparator offset and capacitor mismatch, as well as improve the performance of the successive approximation analog-to-digital converter (SARADC). The dynamic comparator is designed with two preamplifiers and one latch to facilitate high speed, high precision, and low noise. The foreground digital calibration algorithm provides high speed with minimal area consumption. This design is implemented on a 12-bit 30 MS/s SARADC with a standard 0.13 μm Complementary Metal Oxide Semiconductor (CMOS) process. The simulation Nyquist 68.56 dB signal-to-noise-and-distortion ratio (SNDR) and 84.45 dBc spurious free dynamic range (SFDR) at 30 MS/s, differential nonlinearity (DNL) and integral nonlinearity (INL) are within 0.64 Least Significant Bits (LSB) and 1.3 LSB, respectively. The ADC achieves an effective number of bits (ENOB) of 11.08 and a figure-of-merit (FoM) of 39.45 fJ/conv.-step.

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