scholarly journals Newly Designed Electrostatic Wafer Chuck Resulting in Less Particle Contamination on Back Side of Wafers.

Shinku ◽  
1998 ◽  
Vol 41 (3) ◽  
pp. 139-142
Author(s):  
Azusa SIMAMURA ◽  
Nobuo TSUMAKI ◽  
Hiroyuki KITSUNAI ◽  
Tadashi OTAKA
Keyword(s):  
Back Side ◽  
Particle Contamination

A Detailed Study of a Novel Wafer Separation Method for Surface Sensitive MEMS Wafers

2012 ◽  
Vol 1415 ◽  
Author(s):  
K. Malachowski ◽  
S. Severi ◽  
R. Van Hoof ◽  
S. Sangameswaran ◽  
S. Genda ◽  
...  
Keyword(s):  
Process Integration ◽  
Separation Method ◽  
Work Design ◽  
Back Side ◽  
Design Rules ◽  
Micro Electro Mechanical Systems ◽  
Particle Contamination ◽  
Before And After ◽  
Common Technique ◽  
Process Speed

ABSTRACTAbrasive blade dicing is the most common technique for die separation. In this work an alternative dry and non-abrasive die separation method, which is known as "Stealth dicing", is assessed for surface-sensitive MEMS (Micro Electro Mechanical Systems) wafers. The dicing performance and capability of the system is investigated on 200mm full thickness wafers with and without MEMS structures. The diced wafers are analyzed with respect to the silicon cutting quality, possible particle contamination, the condition of functional structures and their mechanical and electrical functionality. In addition the performance and limitations of two different Stealth Dicing Engine (SDE) types, SDE01 and SDE03, are compared to each other with respect to their performance on MEMS wafer dicing.From this work design rules and proper dimensions of the scribe line can be determined. Process integration solutions, describing steps before and after the Stealth dicing process, including the contact-less dicing tape application to the wafer back side and the final die separation method by tape stretching, are presented. It was also found that the SDE03 laser with its outstanding performance in terms of process speed and separation quality can bring a breakthrough for applying this technology for MEMS wafers.

HREM observation of dislocations near room temperature fractures in silicon

1988 ◽  
Vol 46 ◽  
pp. 892-893
Author(s):  
M. H. Rhee ◽  
W. A. Coghlan
Keyword(s):  
Cross Section ◽  
Room Temperature ◽  
Single Crystal Silicon ◽  
Dislocation Nucleation ◽  
Back Side ◽  
Ion Milling ◽  
Crystal Silicon ◽  
Flat Surfaces ◽  
Induced Fractures ◽  
Vicker’S Microhardness

Silicon is believed to be an almost perfectly brittle material with cleavage occurring on {111} planes. In such a material at room temperature cleavage is expected to occur prior to any dislocation nucleation. This behavior suggests that cleavage fracture may be used to produce usable flat surfaces. Attempts to show this have failed. Such fractures produced in semiconductor silicon tend to occur on planes of variable orientation resulting in surfaces with a poor surface finish. In order to learn more about the mechanisms involved in fracture of silicon we began a HREM study of hardness indent induced fractures in thin samples of oxidized silicon.Samples of single crystal silicon were oxidized in air for 100 hours at 1000°C. Two pieces of this material were glued together and 500 μm thick cross-section samples were cut from the combined piece. The cross-section samples were indented using a Vicker's microhardness tester to produce cracks. The cracks in the samples were preserved by thinning from the back side using a combination of mechanical grinding and ion milling.

Field Effect Modulation of Electrocatalytic Hydrogen Evolution at Back-Gated Two-Dimensional MoS2 Electrodes

2019 ◽  
Author(s):  
Yan Wang ◽  
Sagar Udyavara ◽  
Matthew Neurock ◽  
C. Daniel Frisbie
Keyword(s):  
Electric Field ◽  
Hydrogen Evolution ◽  
Active Sites ◽  
Density Functional ◽  
Electrode Materials ◽  
Density Functional Theory Calculations ◽  
Electronic Charge ◽  
Back Side ◽  
Gate Electrode ◽  
Conventional Manner

<div> <div> <div> <p> </p><div> <div> <div> <p>Electrocatalytic activity for hydrogen evolution at monolayer MoS2 electrodes can be enhanced by the application of an electric field normal to the electrode plane. The electric field is produced by a gate electrode lying underneath the MoS2 and separated from it by a dielectric. Application of a voltage to the back-side gate electrode while sweeping the MoS2 electrochemical potential in a conventional manner in 0.5 M H2SO4 results in up to a 140-mV reduction in overpotential for hydrogen evolution at current densities of 50 mA/cm2. Tafel analysis indicates that the exchange current density is correspondingly improved by a factor of 4 to 0.1 mA/cm2 as gate voltage is increased. Density functional theory calculations support a mechanism in which the higher hydrogen evolution activity is caused by gate-induced electronic charge on Mo metal centers adjacent the S vacancies (the active sites), leading to enhanced Mo-H bond strengths. Overall, our findings indicate that the back-gated working electrode architecture is a convenient and versatile platform for investigating the connection between tunable electronic charge at active sites and overpotential for electrocatalytic processes on ultrathin electrode materials.</p></div></div></div><br><p></p></div></div></div>

Identification of Root Cause Failure in Silicon on Insulator Body Contacted nFETs Using Scanning Capacitance Microscopy and Scanning Spreading Resistance Microscopy

2006 ◽  
Author(s):  
J.S. McMurray ◽  
C.M. Molella
Keyword(s):  
The Body ◽  
Silicon On Insulator ◽  
Back Side ◽  
Cross Sectional ◽  
Plan View ◽  
Spreading Resistance ◽  
Scanning Capacitance Microscopy ◽  
Root Cause ◽  
Cross Sectional Imaging ◽  
Active Channel

Abstract Root cause for failure of 90 nm body contacted nFETs was identified using scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM). The failure mechanism was identified using both cross sectional imaging and imaging of the active silicon - buried oxide (BOX) interface in plan view. This is the first report of back-side plan view SCM and SSRM data for SOI devices. This unique plan view shows the root cause for the failure is an under doped link up region between the body contacts and the active channel of the device.

Failure Analysis of Killer Defects and Yield Enhancement of Flat ROM Devices in Wafer Fabrication

2000 ◽  
Author(s):  
Y. N. Hua ◽  
Z. R. Guo ◽  
L. H. An ◽  
Shailesh Redkar
Keyword(s):  
Electron Microscope ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Wafer Fabrication ◽  
X Ray ◽  
Particle Contamination ◽  
Emission Microscopy ◽  
Microscopy Techniques ◽  
Scanning Electron

Abstract In this paper, some low yield cases in Flat ROM device (0.45 and 0.6 µm) were investigated. To find killer defects and particle contamination, KLA, bitmap and emission microscopy techniques were used in fault isolation. Reactive ion etching (RIE) and chemical delayering, 155 Wright Etch, BN+ Etch and scanning electron microscope (SEM) were used for identification and inspection of defects. In addition, energy-dispersive X-ray microanalysis (EDX) was used to determine the composition of the particle or contamination. During failure analysis, seven kinds of killer defects and three killer particles were found in Flat ROM devices. The possible root causes, mechanisms and elimination solutions of these killer defects/particles were also discussed.

Electron Beam Absorbed Current as a Means of Locating Metal Defectivity on 45nm SOI Technology

2010 ◽  
Author(s):  
K. Dickson ◽  
G. Lange ◽  
K. Erington ◽  
J. Ybarra
Keyword(s):  
Electron Beam ◽  
Flip Chip ◽  
Back Side ◽  
Soi Technology

Abstract This paper describes the use of Electron Beam Absorbed Current (EBAC) mapping performed from the back side of the device as a means of locating metallization defects on flip chip 45nm SOI technology.

Failure Analysis of Autoclave-Stressed SRAMs with Aluminum Fuses

1999 ◽  
Author(s):  
Jamey Moss ◽  
Sam Subramanian ◽  
Vince Soorholtz ◽  
Michael Thomas ◽  
Mark Gerber ◽  
...  
Keyword(s):  
Nitric Acid ◽  
Fire Retardant ◽  
Antimony Trioxide ◽  
Back Side ◽  
New Approach ◽  
Eds Analysis ◽  
Plastic Package ◽  
Residual Aluminum ◽  
Rich Material ◽  
Static Ram

Abstract Several hundred units were subjected to autoclave stress as part of the qualification of a new fast static RAM. Many units failed after autoclave stress, and these parts recovered after conventional depotting using nitric acid and a hot plate. Based on the recovery of the units, the failures were determined to be fuse-related because the nitric acid cleared the fuse cavities during depotting. Chemical analysis after thermally extracting the die from the package revealed an antimony-rich material in failing fuse cavities. Source of the antimony was linked to antimony trioxide added to the plastic package as a fire retardant. However, it was unclear whether the antimony-rich material caused the failure or if it was an artifact of thermal depotting. A new approach that did not thermally or chemically alter the fuse cavities was employed to identify the failing fuses. This approach used a combination of back-side grinding, dimpling, and back-side microprobing. The antimony-rich material found in the fuse cavity was confirmed using SEM and TEM-based EDS analysis, and it is believed to be a major contributing factor to fuse failures. However, it is unclear whether the short was caused by the antimony-rich material or by a reaction between that material and residual aluminum (oxide) left in the fuse cavity after the laser blows.

scholarly journals Effects of Thermal Annealing on the Characteristics of High Frequency FBAR Devices

Coatings ◽  
2021 ◽  
Vol 11 (4) ◽  
pp. 397
Author(s):  
Yu-Chen Chang ◽  
Ying-Chung Chen ◽  
Bing-Rui Li ◽  
Wei-Che Shih ◽  
Jyun-Min Lin ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Films ◽  
Thermal Annealing ◽  
Electromechanical Coupling ◽  
Zno Thin Films ◽  
Electromechanical Coupling Coefficient ◽  
Back Side ◽  
Zno Thin Film ◽  
Frequency Responses ◽  
Sputtering System

In this study, piezoelectric zinc oxide (ZnO) thin film was deposited on the Pt/Ti/SiNx/Si substrate to construct the FBAR device. The Pt/Ti multilayers were deposited on SiNx/Si as the bottom electrode and the Al thin film was deposited on the ZnO piezoelectric layer as the top electrode by a DC sputtering system. The ZnO thin film was deposited onto the Pt thin film by a radio frequency (RF) magnetron sputtering system. The cavity on back side for acoustic reflection of the FBAR device was achieved by KOH solution and reactive ion etching (RIE) processes. The crystalline structures and surface morphologies of the films were analyzed by X-ray diffraction (XRD) and field emission scanning electron microscope (FE-SEM). The optimized as-deposited ZnO thin films with preferred (002)-orientation were obtained under the sputtering power of 80 W and sputtering pressure of 20 mTorr. The crystalline characteristics of ZnO thin films and the frequency responses of the FBAR devices can be improved by using the rapid thermal annealing (RTA) process. The optimized annealing temperature and annealing time are 400 °C and 10 min, respectively. Finally, the FBAR devices with structure of Al/ZnO/Pt/Ti/SiNx/Si were fabricated. The frequency responses showed that the return loss of the FBAR device with RTA annealing was improved from −24.07 to −34.66 dB, and the electromechanical coupling coefficient (kt2) was improved from 1.73% to 3.02% with the resonance frequency of around 3.4 GHz.

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