Estimating Balance Uncertainty By Monte Carlo Simulation on a High-Speed Parallel architecture

2017 ◽  
Author(s):  
Peter M. Bidgood
Keyword(s):  
Monte Carlo Simulation ◽  
Monte Carlo ◽  
High Speed ◽  
Parallel Architecture

Investigation of Neutral Particles Using High Speed Camera and Monte-Carlo Simulation in the GAMMA 10 Central-Cell

2007 ◽  
Vol 51 (2T) ◽  
pp. 82-85 ◽  
Author(s):  
Y. Nakashima ◽  
Y. Higashizono ◽  
N. Nishino ◽  
H. Kawano ◽  
M.K. Islam ◽  
...  
Keyword(s):  
Monte Carlo Simulation ◽  
Monte Carlo ◽  
High Speed ◽  
Central Cell ◽  
High Speed Camera ◽  
Neutral Particles

scholarly journals A High-Speed and Low-Offset Dynamic Latch Comparator

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Labonnah Farzana Rahman ◽  
Mamun Bin Ibne Reaz ◽  
Chia Chieu Yin ◽  
Mohammad Marufuzzaman ◽  
Mohammad Anisur Rahman
Keyword(s):  
Monte Carlo Simulation ◽  
Monte Carlo ◽  
Power Dissipation ◽  
High Speed ◽  
Cmos Process ◽  
Clock Frequency ◽  
Analog To Digital ◽  
Offset Voltage ◽  
Simulation Results ◽  
Low Offset

Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that the equivalent input-referred offset voltage is 720 μV with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 μW of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of148.80 μm×59.70 μm.

A very high speed Monte Carlo simulation on DAP

1985 ◽  
Vol 37 (1-3) ◽  
pp. 351-356 ◽  
Author(s):  
S.F. Reddaway ◽  
D.M. Scott ◽  
K.A. Smith
Keyword(s):  
Monte Carlo Simulation ◽  
Monte Carlo ◽  
High Speed ◽  
Very High

A LOW OFFSET COMPARATOR FOR HIGH SPEED LOW POWER ADC

2013 ◽  
Vol 22 (07) ◽  
pp. 1350061 ◽  
Author(s):  
ZHANGMING ZHU ◽  
WEITIE WANG ◽  
YUHENG GUAN ◽  
SHUBIN LIU ◽  
YU XIAO ◽  
...  
Keyword(s):  
Monte Carlo Simulation ◽  
Monte Carlo ◽  
Low Power ◽  
High Speed ◽  
Cmos Process ◽  
Amplifier Circuit ◽  
Offset Cancellation ◽  
Offset Voltage ◽  
Low Offset

A novel low offset, high speed, low power comparator architecture is proposed in this paper. In order to achieve low offset, both offset cancellation and dynamic amplifier techniques are adopted. Active resistors are chosen to implement the static amplifier circuit to obtain reduction in equivalent input referred offset voltage as well as to increase the circuit speed. The comparator is designed in TSMC 0.18 μm CMOS process. Monte Carlo simulation shows that the comparator has the offset voltage as low as 0.3 mV at 1 sigma at 250 MHz while dissipates 342 μW from a 1.8 V supply.

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