scholarly journals A High-Speed and Low-Offset Dynamic Latch Comparator

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Labonnah Farzana Rahman ◽  
Mamun Bin Ibne Reaz ◽  
Chia Chieu Yin ◽  
Mohammad Marufuzzaman ◽  
Mohammad Anisur Rahman
Keyword(s):  
Monte Carlo Simulation ◽  
Monte Carlo ◽  
Power Dissipation ◽  
High Speed ◽  
Cmos Process ◽  
Clock Frequency ◽  
Analog To Digital ◽  
Offset Voltage ◽  
Simulation Results ◽  
Low Offset

Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that the equivalent input-referred offset voltage is 720 μV with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 μW of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of148.80 μm×59.70 μm.

A LOW OFFSET HIGH SPEED COMPARATOR FOR PIPELINE ADC

2013 ◽  
Vol 22 (04) ◽  
pp. 1350018 ◽  
Author(s):  
ZHANGMING ZHU ◽  
HONGBING WU ◽  
GUANGWEN YU ◽  
YANHONG LI ◽  
LIANXI LIU ◽  
...  
Keyword(s):  
Monte Carlo Simulation ◽  
Power Dissipation ◽  
High Speed ◽  
Cmos Process ◽  
Pipeline Adc ◽  
Analog To Digital ◽  
Offset Cancellation ◽  
Reduction Techniques ◽  
Offset Voltage ◽  
Low Offset

A low offset and high speed preamplifier latch comparator is proposed for high-speed pipeline analog-to-digital converters (ADCs). In order to realize low offset, both offset cancellation techniques and kickback noise reduction techniques are adopted. Based on TSMC 0.18 μm 3.3 V CMOS process, Monte Carlo simulation shows that the comparator has a low offset voltage 1.1806 mV at 1 sigma at 125 MHz, with a power dissipation of 413.48 μW.

A LOW OFFSET COMPARATOR FOR HIGH SPEED LOW POWER ADC

2013 ◽  
Vol 22 (07) ◽  
pp. 1350061 ◽  
Author(s):  
ZHANGMING ZHU ◽  
WEITIE WANG ◽  
YUHENG GUAN ◽  
SHUBIN LIU ◽  
YU XIAO ◽  
...  
Keyword(s):  
Monte Carlo Simulation ◽  
Monte Carlo ◽  
Low Power ◽  
High Speed ◽  
Cmos Process ◽  
Amplifier Circuit ◽  
Offset Cancellation ◽  
Offset Voltage ◽  
Low Offset

A novel low offset, high speed, low power comparator architecture is proposed in this paper. In order to achieve low offset, both offset cancellation and dynamic amplifier techniques are adopted. Active resistors are chosen to implement the static amplifier circuit to obtain reduction in equivalent input referred offset voltage as well as to increase the circuit speed. The comparator is designed in TSMC 0.18 μm CMOS process. Monte Carlo simulation shows that the comparator has the offset voltage as low as 0.3 mV at 1 sigma at 250 MHz while dissipates 342 μW from a 1.8 V supply.

A Low Offset Dynamic Comparator with Offset Elimination Circuit

2017 ◽  
Vol 26 (07) ◽  
pp. 1750115
Author(s):  
Cheng Huang ◽  
Zhilun Lin ◽  
Jianhui Wu ◽  
Chao Chen
Keyword(s):  
Monte Carlo Simulation ◽  
Monte Carlo ◽  
Standard Deviation ◽  
Dynamic Comparator ◽  
Offset Voltage ◽  
Simulation Results ◽  
Low Offset

A new dynamic comparator with offset elimination circuit is proposed. The offset elimination circuit decreases the influence of the offset voltage effectively and increases the resolution of the comparator. The simulation results show that, if the pre-set offset voltage is 10[Formula: see text]mV, the offset elimination circuit can decrease to the enough low value, which meets the requirements of the system. The standard deviation of the offset voltage decreases from 7.27[Formula: see text]mV to 1.15[Formula: see text]mV with the utilization of the offset elimination circuit in Monte Carlo simulation.

scholarly journals A 5 Bit 600MS/S Asynchronous Digital Slope ADC with Modified Strong Arm Comparator

2019 ◽  
Vol 9 (1S5) ◽  
pp. 41-44
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Average Power ◽  
Cmos Technology ◽  
Analog To Digital ◽  
Delay Cell ◽  
Offset Voltage ◽  
Static Power ◽  
Cell Sample ◽  
Low Offset

Strong arm comparator has some characteristics like it devours zero static power and yields rail to rail swing. It acquires a positive feedback allowed by two cross coupled pairs of comparators and results a low offset voltage in input differential stage. We modified a strong arm Comparator for high speed without relying on complex calibration Schemes. a 5- bit 600MS/s asynchronous digital slope analog to digital converter (ADS-ADC) with modified strong arm comparator designed in cadence virtuoso at 180nm CMOS technology. The design of SR-Latch using Pseudo NMOS NOR Gate optimizes the speed. Thus delay reduced in select signal generation block. Power dissipation is minimized with lesser transistor count in Strong arm comparator and SR-Latch with maximum sampling speed. The speed of the converter can be improved by resolution. The proposed circuit is 5-bit ADC containing a delay cell, Sample and hold, continuous time comparator, strong arm comparator, Pseudo NMOS SR-Latch and Multiplexer. This 5- bit ADC operates voltage at 1.8 volts and consumes an average power.

A Low-Noise Dynamic Comparator with Offset Calibration for CMOS Image Sensor Architecture

2018 ◽  
Vol 28 (02) ◽  
pp. 1950022
Author(s):  
Arumugam Sathishkumar ◽  
Siddhan Saravanan
Keyword(s):  
High Speed ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Low Noise ◽  
Clock Frequency ◽  
Dynamic Comparator ◽  
Analog To Digital ◽  
Input Capacitance ◽  
Simulation Results ◽  
Output Swing

A low-noise, high-speed, low-input-capacitance switched dynamic comparator (SDC) CMOS image sensor architecture is presented in this paper. The comparator design occupying less area and consuming lesser power is suitable for bank of comparators in CMOS image readouts. The proposed dynamic comparator eliminates the stacking issue related to the conventional comparator and reduces the offset noise further. The need for low-noise, low-power, area-efficient and high-speed flash analog-to-digital converters (ADCs) in many applications today motivated us to design a comparator for ADC. The rail-to-rail output swing is also improved. The input capacitance is reduced by using shared first-stage technique. The comparator is designed with constant [Formula: see text]/[Formula: see text] biasing to suppress the environmental drift. The simulation results from 45-nm and 65-nm CMOS technologies confirm the analysis results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. The maximum clock frequency of the proposed comparator can be increased to 3.5[Formula: see text]GHz and 2.2[Formula: see text]GHz at supply voltages of 1[Formula: see text]V and 0.6[Formula: see text]V, respectively. Simulations are carried out using predictive technology models for 45[Formula: see text]nm and 65[Formula: see text]nm in HSPICE.

scholarly journals Design of Bootstrap Sample and Hold Circuit

2019 ◽  
Vol 8 (4) ◽  
pp. 4053-4057
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Performance Metrics ◽  
Open Loop ◽  
Cmos Process ◽  
Bootstrap Sample ◽  
Analog To Digital ◽  
Sample And Hold ◽  
Higher Power ◽  
The Cost

This paper describes the design and implementation of open loop sample and hold circuit using bootstrap technique, which can be used as front end sampling circuit for high speed analog-to-digital converters. Different design criteria viz. speed, power, resolution, linearity, noise and harmonic analysis have been dealt with. Both theoretical analysis and simulation results are carried out. The bootstrap circuit is designed and then compared in a 0.18μm and 0.35μm CMOS process. It is observed that signal to noise and distortion ratio (SNDR) and effective number of bits (ENOB) are higher for 0.35µm technology. But these advantages are at the cost of higher power dissipation. Hence there exists a trade-off between these performance metrics.

scholarly journals Delta-Sigma Modulator with Relaxed Feedback Timing for High Speed Applications

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1138
Author(s):  
Youngho Jung ◽  
Jooyoung Jeon
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Cmos Process ◽  
Dynamic Element Matching ◽  
Analog To Digital ◽  
Feedback Timing ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Circuit Technique ◽  
Signal Band

In this paper, a ΔΣ analog-to-digital converter (ADC) was designed and measured for broadband and high-resolution applications by applying the simple circuit technique to alleviate the feedback timing of input feed-forward architecture. With the proposed technique, a low-speed comparator and dynamic element matching (DEM) logic can be applied even for high-speed implementation, which helps to decrease power dissipation. Two prototypes using slightly different input branch topologies were fabricated with a 0.18 um 2-poly and 4-metal CMOS process, and measured to demonstrate the effectiveness of the proposed circuit technique. The sampling capacitor and feedback DAC capacitors were separated in prototype A, while they were shared in prototype B. The prototypes achieved 81.2 dB and 72.4 dB of SNDR in a 2.1 MHz signal band, respectively.

A Novel Pre-Amplifier for DTH in Folding and Interpolating ADC

2013 ◽  
Vol 321-324 ◽  
pp. 367-371
Author(s):  
Jing Lei Han ◽  
Wen Lian Zhang ◽  
Zhi Biao Shao
Keyword(s):  
Power Dissipation ◽  
Software Defined Radio ◽  
High Speed ◽  
Low Voltage ◽  
Cmos Technology ◽  
Analog To Digital ◽  
Device Mismatch ◽  
Offset Voltage ◽  
Gain Error ◽  
Input Range

A pre-amplifier for distributed track and hold (DTH) circuit in high speed and high resolution folding and interpolating analog-to-digital converter (ADC) is proposed. This scheme resolves several limitations of conventional differential difference pre-amplifier (DDPA) in low voltage supply, compared to the conventional DDPA, the proposed scheme increases the input range so that all DDPAs of DTH can operate effectively, improves the averaging effect of average network, saves the random offset voltage from device mismatch, decreases the gain error of DTH, reduces the output common-mode (CM) deviation of DTH, and enhances the CM rejection of DTH. Based on SMIC 0.18μm CMOS technology and 1.8V power supply, over the input range, results from spectre shows dummy DDPAs of DTH operate effectively, the offset of output CM voltage of DTH decrease to less than 2mV, gain error decrease to less than 1%, the gain of middle novel pre-amplifier and boundary novel pre-amplifier are both 2.5, bandwidths are all above 1.9GHZ, while power dissipation of each DDPA is 3.22mW. The high CM rejection and low gain error decrease the quantification error effectively, and enhance the performance of ADC. The design meets the requirement of ADC applied to software defined radio (SDR).

AN OPTIMIZED LOW POWER PIPELINE ANALOG-TO-DIGITAL CONVERTER FOR HIGH-SPEED WLAN APPLICATION

2014 ◽  
Vol 23 (05) ◽  
pp. 1450059 ◽  
Author(s):  
MAO YE ◽  
BIN WU ◽  
YONGXU ZHU ◽  
YUMEI ZHOU
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Dynamic Range ◽  
Cmos Process ◽  
Area Network ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Silicon Area ◽  
Analog To Digital

This paper presents the design and implementation of a 11-bit 160 MSPS analog-to-digital converter (ADC) for next generation super high-speed wireless local area network (WLAN) application. The ADC core consists of one front sample and hold stage and four cascades of 2.5 bit pipeline stages with opamp sharing between successive stages. To achieve low power dissipation at 1.2 V supply, a single stage symmetrical amplifier with double transimpedance gain-boosting amplifier is proposed. High speed on-chip reference buffer with replica source follower is also included for linearity performance. The ADC was fabricated in a standard 130-nm CMOS process and an occupied silicon area of 0.95 mm × 1.15 mm. Performance of 73 dB spurious-free-dynamic-range is measured at 160 MS/s with 1 Vpp input signal. The power dissipation of the analog core chip is only 50 mW from a 1.2 V supply.

scholarly journals 1.5mW,14.68V/µS-Low Power and High Speed Comparator Design for ADC Applications

2019 ◽  
Vol 8 (6S4) ◽  
pp. 1322-1326
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Analog To Digital Converters ◽  
Slew Rate ◽  
Two Stage ◽  
Analog To Digital ◽  
Low Offset ◽  
Medical Equipments

Advanced medical equipments embedded with the sensors, analog to digital converters (ADC) and other equipment. Gain amplifier and the comparator are key blocks in ADCs improvement. Comparator is the key element in achieving a low offset and high slew ratein the ADCs, in addition power and speed optimizationdesigns are preferred. To achieve high speed and low power a modified architecture of a comparator is introduced. A 5V two stage comparator is designed to meet the specifications as, offset value <8.4mV, power dissipation <1.5mW and slew rate>14.68V/µS. Cadence Virtuoso tools and SCL 0.18 µm technology parameters are used for design. Designed comparator shows improved slew rate and power consumption in comparison with the existing comparators

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