Joint Resistance to Ram

Author(s):  
Gregory Czarnecki ◽  
Ronald Hinrichsen ◽  
Michele Maxson
Keyword(s):  
2018 ◽  
Vol 28 (4) ◽  
pp. 1-5 ◽  
Author(s):  
Hyung-Seop Shin ◽  
Mark Angelo Diaz ◽  
Zhierwinjay Mezona Bautista ◽  
Satoshi Awaji

2012 ◽  
Vol 2012 (1) ◽  
pp. 001018-001025
Author(s):  
Ahmer Syed ◽  
Christopher J. Berry ◽  
Karthikeyan Dhandapani ◽  
Patrick Thompson ◽  
Seung-Hyun Chae

The miniaturization trend in electronic packaging continues to drive smaller and smaller chip-to-substrate interconnections with no reduction in IC operating temperature or device power in sight. These two factors (current density and temperature) make the electromigration lifetime of chip-to-package interconnections a critical consideration in package design. Of particular interest these days are the “fine pitch copper pillar” structures due to their very small size (30um dia or less). This paper presents interconnection lifetime and metallurgical data on the same which demonstrates the extreme robustness of these joints due largely to their reaching a fully reacted state in which no free solder exists in the conduction path thus providing electromigration performance like that of the base copper and intermetallic compounds. Joint resistance trends observed during stress testing are also discussed.


2020 ◽  
Vol 30 (4) ◽  
pp. 1-4
Author(s):  
Kensuke Kobayashi ◽  
Gen Nishijima ◽  
Akira Uchida ◽  
Munenori Amaya ◽  
Nobuya Banno ◽  
...  

2013 ◽  
Vol 45 ◽  
pp. 165-168 ◽  
Author(s):  
T. Watanabe ◽  
T. Kamata ◽  
T. Maebatake ◽  
R. Teranishi ◽  
T. Kiss ◽  
...  

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