High-Speed Civil Transport Design Space Exploration Using Aerodynamic Response Surface Approximations

2002 ◽  
Vol 39 (2) ◽  
pp. 215-220 ◽  
Author(s):  
Chuck A. Baker ◽  
Bernard Grossman ◽  
Raphael T. Haftka ◽  
William H. Mason ◽  
Layne T. Watson
Keyword(s):  
Response Surface ◽  
High Speed ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Response Surface Approximations

Design Space Exploration for a Ram Inlet Waterjet for High-Speed Propulsion

2021 ◽  
Author(s):  
Filippo Avanzi ◽  
Ernesto Benini ◽  
Fabio Ruaro ◽  
William Gobbo
Keyword(s):  
High Speed ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration

scholarly journals Mapping of Massive Data Processing Systems to FPGA Computers Based on Temporal Partitioning and Design Space Exploration

2007 ◽  
Vol 2 (1) ◽  
pp. 45-54
Author(s):  
Paulo Sérgio Brandão Do Nascimento ◽  
Stelita M. Da Silva ◽  
Jordana L. Seixas ◽  
Remy E. Sant’Anna ◽  
Manoel E. De Lima
Keyword(s):  
Data Processing ◽  
High Speed ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Block Size ◽  
Design Flow ◽  
Massive Data ◽  
Temporal Partitioning ◽  
Massive Data Processing

High parallelism degree is fundamental for high speed massive data processing systems. Modern FPGA devices can provide such parallelism plus flexibility. However, these devices are still limited by their logic block size, memory size, memory bandwidth and configuration time. Temporal partitioning techniques can be a solution for such problems when FPGAs are used to implement large systems. In this case, the system is split into partitions (called contexts), multiplexed in a FPGA, by using reconfiguration techniques. This approach can increase the effective area for system implementation, allowing increase of parallelism in each task that composes the application. However, the necessary reconfiguration time between contexts can cause performance decrease. A possible solution for this is an intensive parallelism exploration of massive data application to compensate for this overhead and improve global performance. This is true for modern FPGA with relatively high reconfiguration speed. In this work, A reconfigurable computer platform and design space exploration techniques are proposed for mapping of such massive data applications, as image processing, in FPGA devices, depending on the application task scheduling. A library with different hardware implementation for a different parallelism degree is used for better adjustment of space/time for each task. Experiments demonstrate the efficiency of this approach when compared to the optimal mapping reached by exhaustive timing search in the complete design space exploration. A design flow is shown based on library components that implements typical tasks used in the domain of applications.

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