scholarly journals Frequency Scaling for High Performance of Low-End Pipelined Processors

2021 ◽  
Vol 6 (2) ◽  
pp. 763-775
Author(s):  
Athanasios Tziouvaras ◽  
Georgios Dimitriou ◽  
Michael Dossis ◽  
Georgios Stamoulis
Keyword(s):  
High Performance ◽  
Frequency Scaling ◽  
Pipelined Processors

Balancing Power And Performance In HPC Clouds

2020 ◽  
Vol 63 (6) ◽  
pp. 880-899
Author(s):  
Lixia Chen ◽  
Jian Li ◽  
Ruhui Ma ◽  
Haibing Guan ◽  
Hans-Arno Jacobsen
Keyword(s):  
Energy Consumption ◽  
High Performance ◽  
Virtual Machines ◽  
Support Vector ◽  
Frequency Scaling ◽  
Vm Placement ◽  
Placement Problem ◽  
Dynamic Voltage ◽  
And Performance ◽  
Save Energy

Abstract With energy consumption in high-performance computing clouds growing rapidly, energy saving has become an important topic. Virtualization provides opportunities to save energy by enabling one physical machine (PM) to host multiple virtual machines (VMs). Dynamic voltage and frequency scaling (DVFS) is another technology to reduce energy consumption. However, in heterogeneous cloud environments where DVFS may be applied at the chip level or the core level, it is a great challenge to combine these two technologies efficiently. On per-core DVFS servers, cloud managers should carefully determine VM placements to minimize performance interference. On full-chip DVFS servers, cloud managers further face the choice of whether to combine VMs with different characteristics to reduce performance interference or to combine VMs with similar characteristics to take better advantage of DVFS. This paper presents a novel mechanism combining a VM placement algorithm and a frequency scaling method. We formulate this VM placement problem as an integer programming (IP) to find appropriate placement configurations, and we utilize support vector machines to select suitable frequencies. We conduct detailed experiments and simulations, showing that our scheme effectively reduces energy consumption with modest impact on performance. Particularly, the total energy delay product is reduced by up to 60%.

Reducing Power and Energy Overhead in Instruction Prefetching for Embedded Processor Systems

2011 ◽  
Vol 2 (4) ◽  
pp. 42-58
Author(s):  
Ji Gu ◽  
Hui Guo
Keyword(s):  
High Performance ◽  
Reducing Power ◽  
Improve Performance ◽  
Embedded Processor ◽  
Ubiquitous Systems ◽  
Low Energy Consumption ◽  
Instruction Prefetching ◽  
Improved Performance ◽  
Power And Energy ◽  
Pipelined Processors

Instruction prefetching is an effective way to improve performance of the pipelined processors. However, existing instruction prefetching schemes increase performance with a significant energy sacrifice, making them unsuitable for embedded and ubiquitous systems where high performance and low energy consumption are all demanded. This paper proposes reducing energy overhead in instruction prefetching by using a simple hardware/software design and an efficient prefetching operation scheme. Two approaches are investigated: Decoded Loop Instruction Cache based Prefetching (DLICP) that is most effective for loop intensive applications, and the enhanced DLICP with the popular existing Next Line Prefetching (NLP) for applications of a moderate number of loops. The experimental results show that both DLICP and the enhanced DLICP deliver improved performance at a much reduced energy overhead.

scholarly journals Autotuning based on frequency scaling toward energy efficiency of blockchain algorithms on graphics processing units

2020 ◽  
Vol 77 (1) ◽  
pp. 263-291 ◽  
Author(s):  
Matthias Stachowski ◽  
Alexander Fiebig ◽  
Thomas Rauber
Keyword(s):  
Energy Efficiency ◽  
Graphics Processing Units ◽  
High Performance ◽  
Frequency Scaling ◽  
Energy Efficient Computing ◽  
Dynamic Voltage ◽  
Automated Optimization ◽  
Graphics Processing ◽  
Performance Computing ◽  
Monitoring Phase

AbstractEnergy-efficient computing is especially important in the field of high-performance computing (HPC) on supercomputers. Therefore, automated optimization of energy efficiency during the execution of a compute-intensive program is desirable. In this article, a framework for the automatic improvement of the energy efficiency on NVIDIA GPUs (graphics processing units) using dynamic voltage and frequency scaling is presented. As application, the mining of crypto-currencies is used, since in this area energy efficiency is of particular importance. The framework first determines the energy-optimal frequencies for each available currency on each GPU of a computer automatically. Then, the mining is started, and during a monitoring phase it is ensured that always the most profitable currency is mined on each GPU, using optimal frequencies. Tests with different GPUs show that the energy efficiency, depending on the GPU and the currency, can be increased by up to 84% compared to the usage of the default frequencies. This in turn almost doubles the mining profit.

scholarly journals A High Performance Adaptive Digital LDO Regulator With Dithering and Dynamic Frequency Scaling for IoT Applications

IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 132200-132211
Author(s):  
Muhammad Asif ◽  
Imran Ali ◽  
Danial Khan ◽  
Muhammad Riaz Ur Rehman ◽  
Qurat- Ul-Ain ◽  
...  
Keyword(s):  
High Performance ◽  
Frequency Scaling ◽  
Dynamic Frequency Scaling ◽  
Iot Applications ◽  
Ldo Regulator ◽  
Dynamic Frequency

Reducing Power and Energy Overhead in Instruction Prefetching for Embedded Processor Systems

2013 ◽  
pp. 323-340
Author(s):  
Ji Gu ◽  
Hui Guo
Keyword(s):  
High Performance ◽  
Reducing Power ◽  
Embedded Processor ◽  
Ubiquitous Systems ◽  
Low Energy Consumption ◽  
Instruction Prefetching ◽  
Improved Performance ◽  
Power And Energy ◽  
Pipelined Processors ◽  
Reducing Energy

Instruction prefetching is an effective way to improve performance of the pipelined processors. However, existing instruction prefetching schemes increase performance with a significant energy sacrifice, making them unsuitable for embedded and ubiquitous systems where high performance and low energy consumption are all demanded. This paper proposes reducing energy overhead in instruction prefetching by using a simple hardware/software design and an efficient prefetching operation scheme. Two approaches are investigated: Decoded Loop Instruction Cache-based Prefetching (DLICP) that is most effective for loop intensive applications, and the enhanced DLICP with the popular existing Next Line Prefetching (NLP) for applications of a moderate number of loops. The experimental results show that both DLICP and the enhanced DLICP deliver improved performance at a much reduced energy overhead.

A High Performance Energy Analyzer for Use in Electron Scanning Microscopy

1969 ◽  
Vol 27 ◽  
pp. 14-15
Author(s):  
A. V. Crewe ◽  
M. Isaacson ◽  
D. Johnson
Keyword(s):  
High Performance ◽  
Vertical Plane ◽  
Median Plane ◽  
Electron Gun ◽  
Uniform Field ◽  
Loss Mechanism ◽  
Electron Scanning Microscopy ◽  
Sector Type ◽  
Double Focusing ◽  
Electron Energy Loss

A double focusing magnetic spectrometer has been constructed for use with a field emission electron gun scanning microscope in order to study the electron energy loss mechanism in thin specimens. It is of the uniform field sector type with curved pole pieces. The shape of the pole pieces is determined by requiring that all particles be focused to a point at the image slit (point 1). The resultant shape gives perfect focusing in the median plane (Fig. 1) and first order focusing in the vertical plane (Fig. 2).

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