scholarly journals On the Design of Punctured Low Density Parity Check Codes for Variable Rate Systems

2017 ◽  
Vol 1 (2) ◽  
pp. 88 ◽  
Author(s):  
Marco Baldi ◽  
Franco Chiaraluce
Keyword(s):  
Ldpc Codes ◽  
The Other ◽  
Variable Rate ◽  
Parity Check ◽  
Pragmatic Approach ◽  
Parity Check Matrix ◽  
Tanner Graph ◽  
Low Density Parity Check ◽  
Check Matrix ◽  
Parity Check Codes

The authors face the problem of designing good LDPC codes for applications requiring variable, that is adaptive, rates. More precisely, the object of the paper is twofold. On one hand, we propose a deterministic (not random) procedureto construct good LDPC codes without constraints on the code dimension and rate. The method is based on the analysis and optimization of the local cycles length in the Tanner graph and gives the designer the chance to control complexity of the designed codes. On the other hand, we present a novel puncturing strategy which acts directly on the parity check matrix of the code, starting from the lowest rate needed, in order to allow the design of higher rate codes avoiding additional complexity of the co/decoding hardware. The efficiency of the proposed solution is tested through a number of numerical simulations. In particular, the puncturing strategy is applied for designing codes with rate variable between 0.715 and 0.906. The designed codes are used in conjunction with M-QAM constellations through a pragmatic approach that, however, yields very promising results.

scholarly journals Regular and Irregular Multiple Serially- Concatenated Multiple-Parity-Check Codes for Wireless Applications

2009 ◽  
Vol 5 (4) ◽  
pp. 140 ◽  
Author(s):  
Marco Baldi ◽  
Giovanni Cancellieri ◽  
Franco Chiaraluce ◽  
Amedeo De Amicis De Amicis
Keyword(s):  
Ldpc Codes ◽  
Mobile Wimax ◽  
Parity Check ◽  
Parity Check Matrix ◽  
Simple Modification ◽  
Tanner Graph ◽  
Wireless Applications ◽  
Check Matrix ◽  
Serially Concatenated ◽  
Parity Check Codes

Multiple Serially-Concatenated Multiple-Parity-Check (M-SC-MPC) codes are a class of structured Low-Density Parity-Check (LDPC) codes, characterized by very simple encoding, that we have recently introduced. This paper evidences how the design of M-SC-MPC codes can be optimized for their usage in wireless applications. For such purpose, we consider some Quasi-Cyclic LDPC codes included in the mobile WiMax standard, and compare their performance with that of M-SCMPC codes having the same parameters. We also present a simple modification of the inner structure of M-SC-MPC codes that can help to improve their error correction performance by introducing irregularity in the parity-check matrix and increasing the length of local cycles in the associated Tanner graph. Our results show that regular and irregular M-SC-MPC codes, so obtained, can achieve very good performance and compare favorably with standard codes.

Pipeline processing in low-density parity-check codes hardware decoder

2011 ◽  
Vol 59 (2) ◽  
pp. 149-155 ◽  
Author(s):  
W. Sułek
Keyword(s):  
Ldpc Codes ◽  
Optimization Method ◽  
Low Density ◽  
Parity Check ◽  
Parity Check Matrix ◽  
Matrix Optimization ◽  
Low Density Parity Check ◽  
Check Matrix ◽  
Pipeline Processing ◽  
Parity Check Codes

Pipeline processing in low-density parity-check codes hardware decoderLow-Density Parity-Check (LDPC) codes are one of the best known error correcting coding methods. This article concerns the hardware iterative decoder for a subclass of LDPC codes that are implementation oriented, known also as Architecture Aware LDPC. The decoder has been implemented in a form of synthesizable VHDL description. To achieve high clock frequency of the decoder hardware implementation - and in consequence high data-throughput, a large number of pipeline registers has been used in the processing chain. However, the registers increase the processing path delay, since the number of clock cycles required for data propagating is increased. Thus in general the idle cycles must be introduced between decoding subiterations. In this paper we study the conditions for necessity of idle cycles and provide a method for calculation the exact number of required idle cycles on the basis of parity check matrix of the code. Then we propose a parity check matrix optimization method to minimize the total number of required idle cycles and hence, maximize the decoder throughput. The proposed matrix optimization by sorting rows and columns does not change the code properties. Results, presented in the paper, show that the decoder throughput can be significantly increased with the proposed optimization method.

scholarly journals Investigation of random-structure regular LDPC codes construction based on progressive edge-growth and algorithms for removal of short cycles

2021 ◽  
Vol 4 (9(112)) ◽  
pp. 46-53
Author(s):  
Viktor Durcek ◽  
Michal Kuba ◽  
Milan Dado
Keyword(s):  
Hamming Distance ◽  
Ldpc Codes ◽  
Ldpc Code ◽  
Error Correcting Codes ◽  
Random Structure ◽  
Parity Check ◽  
Parity Check Matrix ◽  
Tanner Graph ◽  
Check Matrix ◽  
Computer Based

This paper investigates the construction of random-structure LDPC (low-density parity-check) codes using Progressive Edge-Growth (PEG) algorithm and two proposed algorithms for removing short cycles (CB1 and CB2 algorithm; CB stands for Cycle Break). Progressive Edge-Growth is an algorithm for computer-based design of random-structure LDPC codes, the role of which is to generate a Tanner graph (a bipartite graph, which represents a parity-check matrix of an error-correcting channel code) with as few short cycles as possible. Short cycles, especially the shortest ones with a length of 4 edges, in Tanner graphs of LDPC codes can degrade the performance of their decoding algorithm, because after certain number of decoding iterations, the information sent through its edges is no longer independent. The main contribution of this paper is the unique approach to the process of removing short cycles in the form of CB2 algorithm, which erases edges from the code's parity-check matrix without decreasing the minimum Hamming distance of the code. The two cycle-removing algorithms can be used to improve the error-correcting performance of PEG-generated (or any other) LDPC codes and achieved results are provided. All these algorithms were used to create a PEG LDPC code which rivals the best-known PEG-generated LDPC code with similar parameters provided by one of the founders of LDPC codes. The methods for generating the mentioned error-correcting codes are described along with simulations which compare the error-correcting performance of the original codes generated by the PEG algorithm, the PEG codes processed by either CB1 or CB2 algorithm and also external PEG code published by one of the founders of LDPC codes

New Optical Codes Based on Construction of Parity Check Matrix of LDPC Codes

2019 ◽  
Vol 0 (0) ◽  
Author(s):  
Mohammed Amine Tehami ◽  
Chahinaz Kandouci ◽  
Ali Djebbari
Keyword(s):  
Code Division Multiple Access ◽  
Cross Correlation ◽  
Direct Detection ◽  
Ldpc Codes ◽  
Parity Check ◽  
Parity Check Matrix ◽  
Check Matrix ◽  
Eye Pattern ◽  
Balanced Detection ◽  
Code Division Multiple

AbstractIn this paper, new spectral optical codes based on the construction parity check matrix of LDPC codes were designed and implemented in an optical code-division multiple access communication system. Two types optical family codes can be obtained with respectively a cross correlation of {\lambda _c} = 0 and {\lambda _c} = 1. In each case, the codes can either be decoded using the direct detection or the balanced detection. Performance was evaluated by referring to the Q factor, the bit error rate and the eye pattern diagrams using Optisystem 9.0.

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