Low density parity check codes with semi-random parity check matrix

1999 ◽  
Vol 35 (1) ◽  
pp. 38 ◽  
Author(s):  
Li Ping ◽  
W.K. Leung ◽  
Nam Phamdo
Keyword(s):  
Low Density ◽  
Parity Check ◽  
Parity Check Matrix ◽  
Low Density Parity Check ◽  
Check Matrix ◽  
Parity Check Codes

Pipeline processing in low-density parity-check codes hardware decoder

2011 ◽  
Vol 59 (2) ◽  
pp. 149-155 ◽  
Author(s):  
W. Sułek
Keyword(s):  
Ldpc Codes ◽  
Optimization Method ◽  
Low Density ◽  
Parity Check ◽  
Parity Check Matrix ◽  
Matrix Optimization ◽  
Low Density Parity Check ◽  
Check Matrix ◽  
Pipeline Processing ◽  
Parity Check Codes

Pipeline processing in low-density parity-check codes hardware decoderLow-Density Parity-Check (LDPC) codes are one of the best known error correcting coding methods. This article concerns the hardware iterative decoder for a subclass of LDPC codes that are implementation oriented, known also as Architecture Aware LDPC. The decoder has been implemented in a form of synthesizable VHDL description. To achieve high clock frequency of the decoder hardware implementation - and in consequence high data-throughput, a large number of pipeline registers has been used in the processing chain. However, the registers increase the processing path delay, since the number of clock cycles required for data propagating is increased. Thus in general the idle cycles must be introduced between decoding subiterations. In this paper we study the conditions for necessity of idle cycles and provide a method for calculation the exact number of required idle cycles on the basis of parity check matrix of the code. Then we propose a parity check matrix optimization method to minimize the total number of required idle cycles and hence, maximize the decoder throughput. The proposed matrix optimization by sorting rows and columns does not change the code properties. Results, presented in the paper, show that the decoder throughput can be significantly increased with the proposed optimization method.

scholarly journals On the Design of Punctured Low Density Parity Check Codes for Variable Rate Systems

2017 ◽  
Vol 1 (2) ◽  
pp. 88 ◽  
Author(s):  
Marco Baldi ◽  
Franco Chiaraluce
Keyword(s):  
Ldpc Codes ◽  
The Other ◽  
Variable Rate ◽  
Parity Check ◽  
Pragmatic Approach ◽  
Parity Check Matrix ◽  
Tanner Graph ◽  
Low Density Parity Check ◽  
Check Matrix ◽  
Parity Check Codes

The authors face the problem of designing good LDPC codes for applications requiring variable, that is adaptive, rates. More precisely, the object of the paper is twofold. On one hand, we propose a deterministic (not random) procedureto construct good LDPC codes without constraints on the code dimension and rate. The method is based on the analysis and optimization of the local cycles length in the Tanner graph and gives the designer the chance to control complexity of the designed codes. On the other hand, we present a novel puncturing strategy which acts directly on the parity check matrix of the code, starting from the lowest rate needed, in order to allow the design of higher rate codes avoiding additional complexity of the co/decoding hardware. The efficiency of the proposed solution is tested through a number of numerical simulations. In particular, the puncturing strategy is applied for designing codes with rate variable between 0.715 and 0.906. The designed codes are used in conjunction with M-QAM constellations through a pragmatic approach that, however, yields very promising results.

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