scholarly journals CMOS Implementation of 5T SRAM with Low Power Dissipation

2021 ◽  
Author(s):  
Rajesh Kumar ◽  
Swati Gupta
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Processing Unit ◽  
Bottom Line ◽  
Flip Flop ◽  
Physical Description ◽  
Central Processing ◽  
Low Power Dissipation ◽  
Cmos Implementation ◽  
Fast Memory

SRAM is a very fast memory with low power consumption. The main objective of this work is to perform a 64-digit SRAM with 90 nm innovation. Execution depended on a granular perspective. SRAM's base module is similar to an N-MOS inverter, flip-flop, and semiconductor. We design this module according to the configuration rule of the ? format. Using Harvard technology, SRAM can easily retrieve information from memory. To create advanced rational circuits, it is important to see how an SRAM is assembled and how it works. The bottom line is that with 0.12 micron 90nm technology, we are developing a 5T SRAM and we can read and write. It is a fundamental part of a computer's central processing unit. RAM is a building block made up of several circuits. The 64-bit SRAM reader was developed with MICROWIND and DSCH2. With the MICROWIND program, the developer can design and simulate an integrated circuit at the physical description level. DSCH2 allows switching of digital logic design.

scholarly journals A Hardware Approach of a Low-Power IoT Communication Interface by NXP FlexIO Module

2019 ◽  
Vol 25 (6) ◽  
pp. 35-39
Author(s):  
Libor Chrastecky ◽  
Jaromir Konecny ◽  
Martin Stankus ◽  
Michal Prauzek
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Total Power ◽  
Processing Unit ◽  
Embedded Devices ◽  
Communication Interface ◽  
Result Section ◽  
Central Processing ◽  
Total Power Consumption ◽  
Software And Hardware

This article describes implementation possibilities of specialized microcontroller peripherals, as hardware solution for Internet of Things (IoT) low-power communication, interfaces. In this contribution, authors use the NXP FlexIO periphery. Meanwhile, RFC1662 is used as a reference communication standard. Implementation of RFC1662 is performed by software and hardware approaches. The total power consumption is measured during experiments. In the result section, authors evaluate a time-consumption trade-off between the software approach running in Central Processing Unit (CPU) and hardware implementation using NXP FlexIO periphery. The results confirm that the hardware-based approach is effective in terms of power consumption. This method is applicable in IoT embedded devices.

scholarly journals Method for improving ripple reduction during phase shedding in multiphase buck converters for SCADA systems

2021 ◽  
Vol 24 (1) ◽  
pp. 29
Author(s):  
Mini P. Varghese ◽  
A. Manjunatha ◽  
T. V. Snehaprabha
Keyword(s):  
Power Supply ◽  
Integrated Circuit ◽  
Buck Converter ◽  
Multiphase System ◽  
Processing Unit ◽  
Central Processing ◽  
Light Load ◽  
Field Programmable ◽  
Ripple Reduction ◽  
Application Specific Integrated Circuit

In the current digital environment, central processing unit (CPUs), field programmable gate array (FPGAs), application-specific integrated circuit (ASICs), as well as peripherals, are growing progressively complex. On motherboards in many areas of computing, from laptops and tablets to servers and Ethernet switches, multiphase phase buck regulators are seen to be more common nowadays, because of the higher power requirements. This study describes a four-stage buck converter with a phase shedding scheme that can be used to power processors in programmable logic controller (PLCs). The proposed power supply is designed to generate a regulated voltage with minimal ripple. Because of the suggested phase shedding method, this power supply also offers better light load efficiency. For this objective, a multiphase system with phase shedding is modeled in MATLAB SIMULINK, and the findings are validated.

A Novel Approach to Design a 4-Bit Binary Comparator Circuit with Reversible Logic using CDSM Gate

2015 ◽  
Vol 11 (1) ◽  
pp. 36-49
Author(s):  
Vandana Shukla ◽  
O. P. Singh ◽  
G. R. Mishra ◽  
R. K. Tiwari
Keyword(s):  
Low Power ◽  
Power Loss ◽  
Optical Computing ◽  
Logic Gates ◽  
Digital Circuit ◽  
Reversible Logic ◽  
Processing Unit ◽  
Quantum Cost ◽  
Central Processing ◽  
Control Circuits

In the recent scenario of microelectronic industry, the reversible logic is considered as the burgeonic technology for digital circuit designing. It deals with the aim to generate digital circuits with zero power loss characteristics. Optical computing, Nanotechnology, Low power CMOS design and Digital Signal Processing (DSP) processors are leading areas of development with the concept of reversible logic. Researchers have already proposed various subsystems of the computer for the creation of low power loss devices with the help of numerous available reversible logic gates. Here in this paper, the authors have proposed a new reversible gate named as CDSM gate with 4×4 size. This CDSM gate is used to design optimized 4-bit binary comparator. The optimization is improved as compared to the existing designs based on some significant performance parameters such as total number of gates, garbage outputs generated, constant inputs and quantum cost. Comparators are widely used in various computing applications such as counters, convertor, Central Processing Unit (CPU) and control circuits etc. The comparator circuits using reversible logic can be visualized as a low power loss subsystem for the development of improved digital systems.

SMALL-SCALE InGaP/GaAs HETEROJUNCTION BIPOLAR TRANSISTORS FOR HIGH-SPEED AND LOW-POWER INTEGRATED-CIRCUIT APPLICATIONS

2001 ◽  
Vol 11 (01) ◽  
pp. 115-136 ◽  
Author(s):  
TOHRU OKA ◽  
KOJI HIRATA ◽  
HIDEYUKI SUZUKI ◽  
KIYOSHI OUCHI ◽  
HIROYUKI UCHIYAMA ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
High Speed ◽  
Bipolar Transistors ◽  
Small Scale ◽  
Flip Flop ◽  
Base Electrode ◽  
Power Integrated Circuit

Small-scale InGaP/GaAs heterojunction bipolar transistors (HBTs) with high-speed as well as low-current operation are demonstrated. To reduce the emitter size SE and the base-collector capacitance CBC simultaneously, the HBTs are fabricated by using WSi/Ti as the base electrode and by burying SiO 2 in the extrinsic collector region. WSi/Ti metals simplify and facilitate processing to fabricate small base electrodes, and the buried SiO 2 reduces the parasitic CBC under the base electrode. The cutoff frequency fT of 156 GHz and the maximum oscillation frequency f max of 255 GHz were obtained at a collector current Ic of 3.5 mA for the HBT with SE of 0.5 μ m ×4.5 μ m , and fT of 114 GHz and f max of 230 GHz were obtained at IC of 0.9 mA for the HBT with SE of 0.25 μ m ×1.5 μ m . A 1/8 static frequency divider operated at a maximum toggle frequency of 39.5 GHz with a power consumption per flip-flop of 190 mW. A transimpedance amplifier provides a gain of 46.5 dB·Ω with a bandwidth of 41.6 GHz at a power consumption of 150 mW. These results indicate the great potential of our HBTs for high-speed. low power integrated circuit applications.

scholarly journals A Cost-Effective Solution to Improving the Electrical Performance of Metal Contacting Interfaces in IC System under Temperature-Humidity Environment

2019 ◽  
Vol 9 (19) ◽  
pp. 3950
Author(s):  
Li ◽  
Meng ◽  
Shi ◽  
Gao ◽  
Zhang ◽  
...  
Keyword(s):  
Contact Resistance ◽  
Integrated Circuit ◽  
System Reliability ◽  
Cost Effective ◽  
Electrical Performance ◽  
Processing Unit ◽  
Test Results ◽  
Effective Solution ◽  
Central Processing ◽  
Humidity Environment

Temperature-humidity (TH) induced failure mechanism (FM) of metal contacting interfaces in integrated circuit (IC) systems has played a significant role in system reliability issues. This paper focuses on central processing unit (CPU)/motherboard interfaces and studies several factors that are believed to have a great impact on TH performance. They include: Enabling load, surface finish quality, and contacting area. Test vehicles (TVs) of Clarkdale package and of Ibex peak motherboard were designed to measure low level contact resistance (LLCR) for catching any failure. Several sets of design of experiments (DOE) were conducted on 85°C/85% relative humidity and test results were analyzed. A proposal that correlates asperity spots and contact tip design with contact resistance was proposed and thus a cost-effective solution for improving electrical performance under TH was deduced. The proposal has proven to be reasonably effective in practice.

scholarly journals Approximate arithmetic circuits

2020 ◽  
Vol 9 (3) ◽  
pp. 183
Author(s):  
Navabharath Reddy G ◽  
Sruti Setlam ◽  
V. Prakasam ◽  
D. Kiran Kumar
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Integrated Circuit ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Integrated Circuit Design ◽  
Compressor Design ◽  
Low Power Dissipation ◽  
Human Sense ◽  
Error Distance

Low power consumption is the necessity for the integrated circuit design in CMOS technology of nanometerscale. Recent research proves that to achieve low power dissipation, implementation of approximate designs is the best design when compared to accurate designs. In most of the multimedia ap- plications, DSP blocks has been used as the core blocks. Most of the video and image processing algorithms implemented by these DSP blocks, where result will be in the form of image or video for human observing. As human sense of observation isless, the output of the DSP blocks allows being numerically approx- imate instead of being accurate. The concession on numerical exactness allows proposing approximate analysis. In this project approximate adders, approximate compressors and multipliers are proposed. Two approximate adders namely PA1 and PA2 are proposed which are of type TGA which provides better results like PA1 comprises of 14 transistors and 2 error distance, achieves reduction in delay by 64.9 % and reduction in power by 74.33% whereas the TGA1 had 16 transistors and more power dissipation.PA2 comprises of 20 transistors and 2 error distance. Similarly PA2 achieves delay reduction by 51.43%, power gets reduced by 67.2%. PDP is reduced by 61.97 % whereas TGA2 had 22 transistors. Approximate 4-2 compressor was proposed in this project to reduce number of partial produt. The compressor design in circuit level took 30 transistors with 4 errors out of 16 combinations whereas existing compressor design 1took 38 and design 2 took 36 transistors. By using the proposed adder and compressors, approximate 4x4 multiplier is proposed. The proposed multiplier achieves delay 124.56 (ns) and power 29.332 (uW)which is reduced by 68.01% in terms of delay and 95.97 % in terms of power when compared to accurate multiplier.

scholarly journals A TensorFlow Extension Framework for Optimized Generation of Hardware CNN Inference Engines

Technologies ◽  
2020 ◽  
Vol 8 (1) ◽  
pp. 6 ◽  
Author(s):  
Vasileios Leon ◽  
Spyridon Mouselinos ◽  
Konstantina Koliogeorgi ◽  
Sotirios Xydis ◽  
Dimitrios Soudris ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Graphics Processing Unit ◽  
Inference Engine ◽  
Efficient Solutions ◽  
Processing Unit ◽  
Central Processing ◽  
Inference Engines ◽  
Field Programmable ◽  
Hardware Description

The workloads of Convolutional Neural Networks (CNNs) exhibit a streaming nature that makes them attractive for reconfigurable architectures such as the Field-Programmable Gate Arrays (FPGAs), while their increased need for low-power and speed has established Application-Specific Integrated Circuit (ASIC)-based accelerators as alternative efficient solutions. During the last five years, the development of Hardware Description Language (HDL)-based CNN accelerators, either for FPGA or ASIC, has seen huge academic interest due to their high-performance and room for optimizations. Towards this direction, we propose a library-based framework, which extends TensorFlow, the well-established machine learning framework, and automatically generates high-throughput CNN inference engines for FPGAs and ASICs. The framework allows software developers to exploit the benefits of FPGA/ASIC acceleration without requiring any expertise on HDL development and low-level design. Moreover, it provides a set of optimization knobs concerning the model architecture and the inference engine generation, allowing the developer to tune the accelerator according to the requirements of the respective use case. Our framework is evaluated by optimizing the LeNet CNN model on the MNIST dataset, and implementing FPGA- and ASIC-based accelerators using the generated inference engine. The optimal FPGA-based accelerator on Zynq-7000 delivers 93% less memory footprint and 54% less Look-Up Table (LUT) utilization, and up to 10× speedup on the inference execution vs. different Graphics Processing Unit (GPU) and Central Processing Unit (CPU) implementations of the same model, in exchange for a negligible accuracy loss, i.e., 0.89%. For the same accuracy drop, the 45 nm standard-cell-based ASIC accelerator provides an implementation which operates at 520 MHz and occupies an area of 0.059 mm 2 , while the power consumption is ∼7.5 mW.

Onboard Device Encapsulation With Two-Phase Cooling

2017 ◽  
Vol 10 (2) ◽  
Author(s):  
S. J. Young ◽  
D. Janssen ◽  
E. A. Wenzel ◽  
B. M. Shadakofsky ◽  
F. A. Kulacki
Keyword(s):  
Heat Transfer ◽  
Pressure Drop ◽  
Integrated Circuit ◽  
Flow Boiling ◽  
Heat Removal ◽  
Coolant Flow ◽  
Coefficient Of Performance ◽  
Processing Unit ◽  
Two Phase ◽  
Central Processing

Onboard liquid cooling of electronic devices is demonstrated with liquid delivered externally to the point of heat removal through a conformal encapsulation. The encapsulation creates a flat microgap above the integrated circuit (IC) and delivers a uniform inlet coolant flow over the device. The coolant is Novec™ 7200, and the electronics are simulated with a resistance heater on a 1:1 scale. Thermal performance is demonstrated at power densities of ∼1 kW/cm3 in the microgap. Parameters investigated are pressure drop, average device temperature, heat transfer coefficient, and coefficient of performance (COP). Nusselt numbers for gap sizes of 0.25, 0.5, and 0.75 mm are reduced to a dimensionless correlation. With low coolant inlet subcooling, two-phase heat transfer is seen at all mass flows. Device temperatures reach 95 °C for power dissipation of 50–80 W (0.67–1.08 kW/cm3) depending on coolant flow for a gap of 0.5 mm. Coefficients of performance of ∼100 to 70,000 are determined via measured pressure drop and demonstrate a low pumping penalty at the device level within the range of power and coolant flow considered. The encapsulation with microgap flow boiling provides a means for use of higher power central processing unit and graphics processing unit devices and thereby enables higher computing performance, for example, in embedded airborne computers.

Design and CMOS Implementation of a Low Power System-on-Chip Integrated Circuit

2011 ◽  
Vol 121-126 ◽  
pp. 755-759
Author(s):  
Hao Lin Gu ◽  
Wei Wei Shan ◽  
Yun Fan Yu ◽  
Yin Chao Lu
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Cmos Process ◽  
Test Results ◽  
Functional Requirements ◽  
Steady State Current ◽  
Dynamic Voltage ◽  
On Chip ◽  
Cmos Implementation ◽  
Multiple Supply Voltages

A low power 32-bit microcontroller using different kinds of low-power techniques to adapt to the dynamically changing performance demands and power consumption constraints of battery powered applications is designed and tested. Four power domains and six power modes are designed to fulfill low-power targets and meet different functional requirements. Varieties of low power methods such as dynamic voltage and frequency scaling (DVFS), multiple supply voltages (MSV), power gating (PG) and so on are applied. A novel zero steady-state current POR circuit which makes excellent performance in the chip’s OFF mode is also integrated. The SoC occupies 20 mm2 in a 0.18 um, 1.8 V nominal-supply, CMOS process. Test results show that the microcontroller works normally at the frequency of 70MHz and performs well in different power modes. Yet it only consumes 1.67μA leakage current in the OFF mode.

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