Hardware-Accelerated Energy-Efficient Synchronization and Communication for Ultra-Low-Power Tightly Coupled Clusters

2019 ◽  
Author(s):  
Florian Glaser ◽  
Germain Haugou ◽  
Davide Rossi ◽  
Qiuting Huang ◽  
Luca Benini
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Coupled Clusters ◽  
Ultra Low Power ◽  
Tightly Coupled

scholarly journals A Simulation Study of a Gate-All-Around Nanowire Transistor with a Core–Insulator

Micromachines ◽  
2020 ◽  
Vol 11 (2) ◽  
pp. 223 ◽  
Author(s):  
Yannan Zhang ◽  
Ke Han ◽  
and Jiawei Li
Keyword(s):  
Metal Oxide ◽  
Low Power ◽  
Energy Efficient ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Future Generation ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Ultra Low Power

Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient and portable. In the pursuit of smaller and faster devices, researchers and scientists have worked out a number of ways to further lower the leaking current of MOSFETs (Metal oxide semiconductor field effect transistor). Nanowire structure is now regarded as a promising candidate of future generation of logical devices due to its ultra-low off-state leaking current compares to FinFET. However, the potential of nanowire in terms of off-state current has not been fully discovered. In this article, a novel Core–Insulator Gate-All-Around (CIGAA) nanowire has been proposed, investigated, and simulated comprehensively and systematically based on 3D numerical simulation. Comparisons are carried out between GAA and CIGAA. The new CIGAA structure exhibits low off-state current compares to that of GAA, making it a suitable candidate of future low-power and energy-efficient devices.

Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology

Circuit World ◽  
2020 ◽  
Vol 46 (3) ◽  
pp. 183-192
Author(s):  
Muhammad Yasir Faheem ◽  
Shun'an Zhong ◽  
Xinghua Wang ◽  
Muhammad Basit Azeem
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Supply Voltage ◽  
Main Idea ◽  
Cost Effective ◽  
Cmos Technology ◽  
Sar Adc ◽  
Ultra Low Power ◽  
Content Type ◽  
Analogue To Digital

Purpose Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC. Design/methodology/approach A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration. Findings The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms. Originality/value The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

scholarly journals Exploiting Data-dependencies in Ultra Low-power DSP Arithmetic

VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 349-363
Author(s):  
V. A. Bartlett ◽  
E. Grass
Keyword(s):  
Energy Efficiency ◽  
Energy Consumption ◽  
Low Power ◽  
Energy Efficient ◽  
Dynamic Logic ◽  
Low Power Consumption ◽  
Ultra Low Power ◽  
Data Dependencies ◽  
Simulation Results ◽  
Asynchronous Environments

Strategies for the design of ultra low power multipliers and multiplier-accumulators are reported. These are optimized for asynchronous applications being able to take advantage of data-dependent computation times. Nevertheless, the low power consumption can be obtained in both synchronous and asynchronous environments. Central to the energy efficiency is a dynamic-logic technique termed Conditional Evaluation which is able to exploit redundancies within the carry-save array and deliver energy consumption which is also heavily data-dependent.Energy efficient adaptations for handling two's complement operands are introduced. Area overheads of the proposed designs are estimated and transistor level simulation results of signed and unsigned multipliers as well as a signed multiplier-accumulator are given.Normalized comparisons with other designs show our approach to use less energy than other published multipliers.

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