Design space exploration of FPGA accelerators for convolutional neural networks

2017 ◽  
Author(s):  
Atul Rahman ◽  
Sangyun Oh ◽  
Jongeun Lee ◽  
Kiyoung Choi
Keyword(s):  
Neural Networks ◽  
Convolutional Neural Networks ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration

scholarly journals Design space exploration of Convolutional Neural Networks based on Evolutionary Algorithms

2017 ◽  
Vol 3 (1) ◽  
Author(s):  
Abeer Al-Hyari ◽  
Shawki Areibi
Keyword(s):  
Neural Networks ◽  
Genetic Algorithms ◽  
Evolutionary Algorithms ◽  
Convolutional Neural Networks ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Handwritten Digit ◽  
Fully Connected ◽  
The Given

This paper proposes a framework for design space exploration ofConvolutional Neural Networks (CNNs) using Genetic Algorithms(GAs). CNNs have many hyperparameters that need to be tunedcarefully in order to achieve favorable results when used for imageclassification tasks or similar vision applications. Genetic Algorithmsare adopted to efficiently traverse the huge search spaceof CNNs hyperparameters, and generate the best architecture thatfits the given task. Some of the hyperparameters that were testedinclude the number of convolutional and fully connected layers, thenumber of filters for each convolutional layer, and the number ofnodes in the fully connected layers. The proposed approach wastested using MNIST dataset for handwritten digit classification andresults obtained indicate that the proposed approach is able to generatea CNN architecture with validation accuracy up to 96.66% onaverage.

scholarly journals CNN2Gate: An Implementation of Convolutional Neural Networks Inference on FPGAs with Automated Design Space Exploration

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2200
Author(s):  
Alireza Ghaffari ◽  
Yvon Savaria
Keyword(s):  
Machine Learning ◽  
Neural Networks ◽  
Convolutional Neural Networks ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Automatic Synthesis ◽  
Software Libraries ◽  
Learning Software ◽  
High Level

Convolutional Neural Networks (CNNs) have a major impact on our society, because of the numerous services they provide. These services include, but are not limited to image classification, video analysis, and speech recognition. Recently, the number of researches that utilize FPGAs to implement CNNs are increasing rapidly. This is due to the lower power consumption and easy reconfigurability that are offered by these platforms. Because of the research efforts put into topics, such as architecture, synthesis, and optimization, some new challenges are arising for integrating suitable hardware solutions to high-level machine learning software libraries. This paper introduces an integrated framework (CNN2Gate), which supports compilation of a CNN model for an FPGA target. CNN2Gate is capable of parsing CNN models from several popular high-level machine learning libraries, such as Keras, Pytorch, Caffe2, etc. CNN2Gate extracts computation flow of layers, in addition to weights and biases, and applies a “given” fixed-point quantization. Furthermore, it writes this information in the proper format for the FPGA vendor’s OpenCL synthesis tools that are then used to build and run the project on FPGA. CNN2Gate performs design-space exploration and fits the design on different FPGAs with limited logic resources automatically. This paper reports results of automatic synthesis and design-space exploration of AlexNet and VGG-16 on various Intel FPGA platforms.

scholarly journals Improving Performance Estimation for Design Space Exploration for Convolutional Neural Network Accelerators

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 520
Author(s):  
Martin Ferianc ◽  
Hongxiang Fan ◽  
Divyansh Manocha ◽  
Hongyu Zhou ◽  
Shuanglong Liu ◽  
...  
Keyword(s):  
Neural Networks ◽  
Language Processing ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Prediction Method ◽  
Gaussian Process Regression ◽  
Performance Estimation ◽  
Estimation Accuracy ◽  
Accurate Estimation

Contemporary advances in neural networks (NNs) have demonstrated their potential in different applications such as in image classification, object detection or natural language processing. In particular, reconfigurable accelerators have been widely used for the acceleration of NNs due to their reconfigurability and efficiency in specific application instances. To determine the configuration of the accelerator, it is necessary to conduct design space exploration to optimize the performance. However, the process of design space exploration is time consuming because of the slow performance evaluation for different configurations. Therefore, there is a demand for an accurate and fast performance prediction method to speed up design space exploration. This work introduces a novel method for fast and accurate estimation of different metrics that are of importance when performing design space exploration. The method is based on a Gaussian process regression model parametrised by the features of the accelerator and the target NN to be accelerated. We evaluate the proposed method together with other popular machine learning based methods in estimating the latency and energy consumption of our implemented accelerator on two different hardware platforms targeting convolutional neural networks. We demonstrate improvements in estimation accuracy, without the need for significant implementation effort or tuning.

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