BandiTS: Dynamic timing speculation using multi-armed bandit based optimization

Author(s):  
Jeff Jun Zhang ◽  
Siddharth Garg
Keyword(s):  
2016 ◽  
Vol 2 ◽  
pp. e79 ◽  
Author(s):  
Naga Durga Prasad Avirneni ◽  
Prem Kumar Ramesh ◽  
Arun K. Somani

Timing Speculation (TS) is a widely known method for realizing better-than-worst-case systems. Aggressive clocking, realizable by TS, enable systems to operate beyond specified safe frequency limits to effectively exploit the data dependent circuit delay. However, the range of aggressive clocking for performance enhancement under TS is restricted by short paths. In this paper, we show that increasing the lengths of short paths of the circuit increases the effectiveness of TS, leading to performance improvement. Also, we propose an algorithm to efficiently add delay buffers to selected short paths while keeping down the area penalty. We present our algorithm results for ISCAS-85 suite and show that it is possible to increase the circuit contamination delay by up to 30% without affecting the propagation delay. We also explore the possibility of increasing short path delays further by relaxing the constraint on propagation delay and analyze the performance impact.


2019 ◽  
Vol 9 (2) ◽  
pp. 17 ◽  
Author(s):  
Roberto Giorgio Rizzo ◽  
Andrea Calimera

Adaptive Voltage Over-Scaling can be applied at run-time to reach the best tradeoff between quality of results and energy consumption. This strategy encompasses the concept of timing speculation through some level of approximation. How and on which part of the circuit to implement such approximation is an open issue. This work introduces a quantitative comparison between two complementary strategies: Algorithmic Noise Tolerance and Approximate Error Detection. The first implements a timing speculation by means approximate computing, while the latter exploits a more sophisticated approach that is based on the approximation of the error detection mechanism. The aim of this study was to provide both a qualitative and quantitative analysis on two real-life digital circuits mapped onto a state-of-the-art 28-nm CMOS technology.


Author(s):  
Atif Yasin ◽  
Jeff Jun Zhang ◽  
Hu Chen ◽  
Siddharth Garg ◽  
Sanghamitra Roy ◽  
...  
Keyword(s):  

Author(s):  
Brian Greskamp ◽  
Lu Wan ◽  
Ulya R. Karpuzcu ◽  
Jeffrey J. Cook ◽  
Josep Torrellas ◽  
...  
Keyword(s):  

Author(s):  
Shan Shen ◽  
Liang Pang ◽  
Tianxiang Shao ◽  
Ming Ling ◽  
Xiao Shi ◽  
...  

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