scholarly journals Reduction the effects of opamp finite gain and offset voltage in LDI termination with a minus one half delay of SC ladder filters

2006 ◽  
Vol 3 (1) ◽  
pp. 45-54 ◽  
Author(s):  
Nikolay Radev ◽  
Kantcho Ivanov
Keyword(s):  
Combined Approach ◽  
First Order ◽  
Op Amp ◽  
Phase Errors ◽  
Offset Voltage ◽  
Dc Gain ◽  
Gain Errors ◽  
Finite Gain ◽  
Discrete Integrator

In this paper a combined approach for reducing the effects of op amp imperfections (finite gain A and offset voltage VOS) in first-order SC cell, realizing LDI (loss less discrete integrator) termination with a minus one half delay is presented. First, the conventional integrator is replaced with gain- and offset-compensated (GOC) integrator. Next, the gain errors m(?) and the phase errors ?(?) are further reduced by using the precise op amp gain approach in the GOC structure. The variation of the dc gain A from its nominal value A0 is taken into account.

scholarly journals A Novel Offset and Finite-Gain Compensated Switched-Capacitor Amplifier with Input Correlated Level Shifting

Electronics ◽  
2019 ◽  
Vol 8 (9) ◽  
pp. 986
Author(s):  
Yan Chen ◽  
Yousheng Chen ◽  
Yan Guo ◽  
Chunxia Li
Keyword(s):  
Cmos Technology ◽  
Double Sampling ◽  
Switched Capacitor ◽  
Dc Offset ◽  
Op Amp ◽  
Correlated Double Sampling ◽  
Gain Error ◽  
Dc Gain ◽  
Finite Gain ◽  
Correlated Level Shifting

A novel offset and finite-gain compensated differential switched-capacitor(SC) amplifier is presented. Incorporating the correlated double sampling (CDS) technique and input correlated level shifting (CLS) technique together, the DC offset and DC gain error of SC amplifier are further reduced by a factor of op-amp DC gain compared with the conventional offset and finite-gain compensated SC amplifier. The effectiveness of the new scheme has been analyzed and verified by extensive simulations. An SC amplifier with the proposed scheme is designed in 130 nm CMOS technology. Simulated results show that with an op-amp having a low DC gain of 30 dB and an input offset of 10 mV, the proposed SC amplifier achieves an output offset and DC-gain error of 154 µV and 0.05%, respectively, which are significantly improved compared with 1.155 mV and 0.42% achieved in the conventional SC amplifier.

Study of the Mainlobe Misorientation of the First-Order Steerable Differential Array in the Presence of Microphone Gain and Phase Errors

2014 ◽  
Vol 21 (6) ◽  
pp. 667-671 ◽  
Author(s):  
Xiaoguang Wu ◽  
Huawei Chen ◽  
Jianjiang Zhou ◽  
Tianwen Guo
Keyword(s):  
First Order ◽  
Phase Errors

A 1-mm2 CMOS-pipelined ADC with integrated folded cascode operational amplifier

2020 ◽  
Vol 37 (4) ◽  
pp. 205-213
Author(s):  
Norhamizah Idros ◽  
Zulfiqar Ali Abdul Aziz ◽  
Jagadheswaran Rajendran
Keyword(s):  
Operational Amplifier ◽  
Open Loop ◽  
Cmos Process ◽  
Silicon Area ◽  
Content Type ◽  
Op Amp ◽  
Dc Gain ◽  
Input Range ◽  
Folded Cascode ◽  
The Impact

Purpose The purpose of this paper is to demonstrate the acceptable performance by using the limited input range towards lower open-loop DC gain operational amplifier (op-amp) of an 8-bit pipelined analog-to-digital converter (ADC) for mobile communication application. Design/methodology/approach An op-amp with folded cascode configuration is designed to provide the maximum open-loop DC gain without any gain-boosting technique. The impact of low open-loop DC gain is observed and analysed through the results of pre-, post-layout simulations and measurement of the ADC. The fabrication process technology used is Silterra 0.18-µm CMOS process. The silicon area by the ADC is 1.08 mm2. Findings Measured results show the differential non-linearity (DNL) error, integral non-linearity (INL) error, signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) are within −0.2 to +0.2 LSB, −0.55 LSB for 0.4 Vpp input range, 22 and 27 dB, respectively, with 2 MHz input signal at the rate of 64 MS/s. The static power consumption is 40 mW with a supply voltage of 1.8 V. Originality/value The experimental results of ADC showed that by limiting the input range to ±0.2 V, this ADC is able to give a good reasonable performance. Open-loop DC gain of op-amp plays a critical role in ADC performance. Low open-loop DC gain results in stage-gain error of residue amplifier and, thus, leads to nonlinearity of output code. Nevertheless, lowering the input range enhances the linearity to ±0.2 LSB.

Fast-settling CMOS Op-Amp with improved DC-gain

2011 ◽  
Vol 70 (3) ◽  
pp. 283-292 ◽  
Author(s):  
Ali Dadashi ◽  
Shamin Sadrafshari ◽  
Khayrollah Hadidi ◽  
Abdollah Khoei
Keyword(s):  
Op Amp ◽  
Dc Gain ◽  
Fast Settling

High Performance Analysis of CDS Delta-Sigma ADC in 45-Nanometer Regime

2014 ◽  
Vol 13 (01) ◽  
pp. 1450003
Author(s):  
Bhanupriya Bhargava ◽  
Pradeep Kumar Sharma ◽  
Shyam Akashe
Keyword(s):  
High Speed ◽  
Flicker Noise ◽  
Supply Voltage ◽  
Frequency Noise ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Op Amp ◽  
Offset Voltage ◽  
Delta Sigma

In this paper, a correlated double sampling (CDS) technique is proposed in the design of a delta sigma analog-to-digital converter (ADC). These CDS techniques are very effective for the compensation of the nonidealities in switched-capacitor (SC) circuits, such as charge injection, clock feed-through, operational amplifier (op-amp) input-referred offset and finite op-amp gain. An improved compensation scheme is proposed to attain continuous compensation of clock feed-through and offset in SC integrators. Both high-speed and low-power operation is achieved without compromising the accuracy requirement. Also this CDS delta sigma ADC is the most promising circuit for analog to digital converter because this circuit reduces noise due to drift and low frequency noise such as flicker noise and offset voltage and also boosts the gain performance of the amplifier. Further, the simulation results of this circuit are verified on using a "cadence virtuoso tool" using spectre at 45 nm technology with supply voltage 0.7 V.

scholarly journals A comparative analysis of two gain- and offset-compensated switched-capacitor integrators

2002 ◽  
Vol 15 (2) ◽  
pp. 295-305
Author(s):  
Nikolay Radev ◽  
Kantcho Ivanov
Keyword(s):  
High Performance ◽  
Building Blocks ◽  
Switched Capacitor ◽  
Central Frequency ◽  
High Q ◽  
Offset Voltage ◽  
Dc Gain ◽  
Band Pass ◽  
Analytical Expressions ◽  
The Ideal

Two high-performance switched-capacitor (SC) integrators which use different approaches for the compensation of the operational amplifier finite dc gain and offset voltage are considered. Analytical expressions for the gain, phase and offset voltage errors of the Baschirotto-90 integrator are derived and compared with the corresponding errors of the Shafeeu-91 integrator. Both the integrators are used as building blocks of a high-Q band pass SC biquad. The resultant filters are compared in terms of the percent deviations from the ideal case of the central frequency and the quality factor. Subsequently, the slight shift in the frequency response of the biquad with Shafeeu-91 integrator is eliminated by modifying the values of two capacitors .

A New Sub-1 Volt 17ppm/°C Offset-Insensitive Resistorless Switched-Capacitor Bandgap Voltage Reference

2020 ◽  
pp. 2150029
Author(s):  
Emad Ebrahimi ◽  
Maliheh Arabnasery
Keyword(s):  
Process Variations ◽  
Voltage Divider ◽  
Cmos Technology ◽  
Reference Voltage ◽  
Cmos Process ◽  
Switched Capacitor ◽  
Voltage Reference ◽  
Op Amp ◽  
Offset Voltage ◽  
Bandgap Voltage Reference

A new PVT compensated voltage reference is presented by using switched-capacitor (S.C.) technique. In the proposed bandgap voltage reference (BGR), a p–n junction is biased with different currents during two different phases and required PTAT and CTAT voltages generated and held by two capacitors. Using a capacitive voltage divider, the PTAT voltage is weighted such that the sub-1V bandgap voltage is achievable. In order to cancel the effect of op-amp offset and to relax the design of op-amp, the offset voltage of the op-amp is sampled by a capacitor during a specified phase and inversely is added to the final bandgap voltage in next phase. The analysis of the proposed S.C. BGR is supplemented by simulation of a 0.5-V BGR with 28[Formula: see text][Formula: see text][Formula: see text]W power consumption in a standard 0.18[Formula: see text][Formula: see text][Formula: see text]m CMOS technology. Simulation results show that the average temperature coefficient of the S.C. BGR is 17[Formula: see text]ppm/∘C and it is robust against the process variations. Applying an arbitrary 100-mV op-amp offset results in a lower than 1.1[Formula: see text]mV deviation in generated reference voltage. Due to the better matching of MIM capacitors in CMOS process (rather than resistors used in conventional BGR) the proposed S.C. bandgap provides good accuracy without any post trimming. Monte–Carlo analysis shows that [Formula: see text]/[Formula: see text] of the generated reference voltage is as low as 0.7%. The sensitivity of the proposed BGR to supply variation is also less than 1%/V.

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