scholarly journals NBT stress and radiation related degradation and underlying mechanisms in power VDMOSFETs

2018 ◽  
Vol 31 (3) ◽  
pp. 367-388 ◽  
Author(s):  
Vojkan Davidovic ◽  
Danijel Dankovic ◽  
Snezana Golubovic ◽  
Snezana Djoric-Veljkovic ◽  
Ivica Manic ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Spontaneous Recovery ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Stress Effects ◽  
Underlying Mechanisms ◽  
Applied Stresses ◽  
Oxide Trapped Charge ◽  
Harsh Conditions ◽  
Insight Into

In this paper we provide an overview of instabilities observed in commercial power VDMOSFETs subjected to irradiation, NBT stress, and to consecutive exposure to them. The results have indicated that irradiation of previously NBT stressed devices leads to additional threshold voltage shift, while NBT stress effects in previously irradiated devices depend on the gate bias applied during irradiation and on the total dose received. This points to the importance of the order of applied stresses, indicating that for proper insight into the prediction of device behaviour not only harsh conditions, but also the order of exposure have to be considered. It has also been shown that changes in the densities of oxide trapped charge and interface traps during spontaneous recovery after each of applied stresses can be significant, thus leading to additional instability, even though the threshold voltage seems to remain stable, pointing to the need for clarifying the responsible mechanisms.

1700V, 5.5mOhm-cm2 4H-SiC DMOSFET with Stable 225°C Operation

2014 ◽  
Vol 778-780 ◽  
pp. 903-906 ◽  
Author(s):  
Kevin Matocha ◽  
Kiran Chatty ◽  
Sujit Banerjee ◽  
Larry B. Rowland
Keyword(s):  
High Temperature ◽  
Temperature Stress ◽  
High Temperatures ◽  
Threshold Voltage ◽  
Room Temperature ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Device Reliability ◽  
Bias Temperature Stress ◽  
High Temperature Operation

We report a 1700V, 5.5mΩ-cm24H-SiC DMOSFET capable of 225°C operation. The specific on-resistance of the DMOSFET designed for 1200V applications is 8.8mΩ-cm2at 225°C, an increase of only 60% compared to the room temperature value. The low specific on-resistance at high temperatures enables a smaller die size for high temperature operation. Under a negative gate bias temperature stress (BTS) at VGS=-15 V at 225°C for 20 minutes, the devices show a threshold voltage shift of ΔVTH=-0.25 V demonstrating one of the key device reliability requirements for high temperature operation.

Research on Threshold Voltage Instability in SiC MOSFET Devices with Precision Measurement

2019 ◽  
Vol 954 ◽  
pp. 133-138
Author(s):  
Ao Liu ◽  
Song Bai ◽  
Run Hua Huang ◽  
Tong Tong Yang ◽  
Hao Liu
Keyword(s):  
Threshold Voltage ◽  
Precision Measurement ◽  
Gate Dielectric ◽  
Interface Traps ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Experimental Platform ◽  
Bias Stress ◽  
Voltage Instability ◽  
Voltage Drift

The mechanism of threshold voltage shift was studied. It is believed that the instability in threshold voltage during gate bias stress is due to capture of electrons by the SiC/gate dielectric interface traps and the gate dielectric near interface traps. New experimental platform was designed and built successfully. When positive stress or negative stress is applied to the gate, the change of threshold voltage occur immediately. After stress removal, the recovery of the threshold voltage occur soon. The change and recovery of threshold voltage are very sensitive to time. In order to get accurate threshold voltage drift data after high-temperature gate bias experiment, test of threshold voltage must be carried out immediately after the experiment.

Novel Method for Evaluation of Negative Bias Temperature Instability of SiC MOSFETs

2019 ◽  
Vol 963 ◽  
pp. 749-752
Author(s):  
Jose Ortiz Gonzalez ◽  
Olayiwola Alatise ◽  
Philip A. Mawby
Keyword(s):  
Threshold Voltage ◽  
High Reliability ◽  
Gate Oxide ◽  
Gate Bias ◽  
Power Devices ◽  
Threshold Voltage Shift ◽  
Temperature Instability ◽  
Power Semiconductor ◽  
Bias Temperature Instability ◽  
Novel Method

The material properties of SiC make SiC power devices a superior alternative to the conventional Si power devices. However, the reliability of the gate oxide has been a major concern, limiting the adoption of SiC power MOSFETs as the power semiconductor of choice in applications which demand a high reliability. The threshold voltage (VTH) shift caused by Bias Temperature Instability (BTI) has focused the attention of different researchers, with multiple publications on this topic. This paper presents a novel method for evaluating the threshold voltage shift due to negative gate bias and its recovery when the gate bias stress is removed. This method could enable gate oxide reliability assessment techniques and contribute to new qualification methods.

Negative threshold voltage shift for LTPS TFTs under x-ray irradiation and gate bias

2019 ◽  
Vol 34 (9) ◽  
pp. 095012 ◽  
Author(s):  
Ya-Hsiang Tai ◽  
Shan Yeh ◽  
Po-Chun Chan ◽  
Yi-Shen Li ◽  
Shih-Hsuan Huang ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
X Ray

Performance of ZnO TFTs with AlN as Insulator

2007 ◽  
Vol 1035 ◽  
Author(s):  
Maria Merlyne De Souza ◽  
Richard B Cross ◽  
Suhas Jejurikar ◽  
K P Adhi
Keyword(s):  
Surface Roughness ◽  
Threshold Voltage ◽  
Rf Sputtering ◽  
Interface States ◽  
Aluminium Nitride ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Positive Threshold ◽  
The Stability

AbstractThe performance of ZnO TFTs fabricated via RF sputtering, with Aluminium Nitride (AlN) as the underlying insulator are reported. The surface roughness of ZnO with AlN is lower than that with SiN by at least 5 times, and that with SiO2 by 30 times. The resulting mobility for the three insulators AlN, SiN, SiO2 using identical process is found to be 3, 0.2-0.7 and 0.1-0.25 cm2/Vs respectively. There does not appear to be any corresponding improvement in the stability of the AlN devices. The devices demonstrate significant positive threshold voltage shift with positive gate bias and negative threshold voltage shift with negative gate bias. The underlying cause is surmised to be ultra-fast interface states in combination with bulk traps in the ZnO.

Effect of Phosphorus Doped Poly Annealing on Threshold Voltage Stability and Thermal Oxide Reliability in 4H-SiC MOSFET

2020 ◽  
Vol 1004 ◽  
pp. 554-558
Author(s):  
Kwangwon Lee ◽  
Young Ho Seo ◽  
Taeseop Lee ◽  
Kyeong Seok Park ◽  
Martin Domeij ◽  
...  
Keyword(s):  
High Temperature ◽  
Threshold Voltage ◽  
Gate Oxide ◽  
Gate Bias ◽  
Annealed Condition ◽  
Threshold Voltage Shift ◽  
Bias Stress ◽  
Phosphorus Doped ◽  
Gate Bias Stress ◽  
Gate Oxide Integrity

We have investigated the effect of high temperature annealing of phosphorus doped poly on gate oxide integrity and device reliability. In NMOS capacitance analysis, unstable flat band voltage characteristics and lower oxide breakdown electric field were observed in wafers which received high temperature poly annealing at 1100 °C. Gate oxide integrity (GOI/Vramp) tests and time dependent dielectric breakdown (TDDB) tests were performed to evaluate wafer level reliability. Degraded GOI characteristics and poor gate oxide lifetime were obtained for the high temperature poly annealed condition. To evaluate package level reliability, high temperature gate bias (HTGB) stress tests were conducted. Some samples failed in positive gate bias stress and more severe negative threshold voltage shift was observed in negative gate bias stress for the high temperature poly annealed condition.

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