scholarly journals An extended Green-Sasao hierarchy of canonical ternary Galois forms and Universal Logic Modules

2017 ◽  
Vol 30 (1) ◽  
pp. 49-66
Author(s):  
Anas Al-Rabadi
Keyword(s):  
Logic Synthesis ◽  
Galois Field ◽  
Input Output ◽  
Universal Logic ◽  
Binary Case ◽  
Sum Of Products ◽  
Logic Modules ◽  
The Many ◽  
Logic Functions ◽  
Spectral Transforms

A new extended Green-Sasao hierarchy of families and forms with a new sub-family for many-valued Reed-Muller logic is introduced. Recently, two families of binary canonical Reed-Muller forms, called Inclusive Forms (IFs) and Generalized Inclusive Forms (GIFs) have been proposed, where the second family was the first to include all minimum Exclusive Sum-Of-Products (ESOPs). In this paper, we propose, analogously to the binary case, two general families of canonical ternary Reed-Muller forms, called Ternary Inclusive Forms (TIFs) and their generalization of Ternary Generalized Inclusive Forms (TGIFs), where the second family includes minimum Galois Field Sum-Of-Products (GFSOPs) over ternary Galois field GF(3). One of the basic motivations in this work is the application of these TIFs and TGIFs to find the minimum GFSOP for many-valued input-output functions within logic synthesis, where a GFSOP minimizer based on IF polarity can be used to minimize the many-valued GFSOP expression for any given function. The realization of the presented S/D trees using Universal Logic Modules (ULMs) is also introduced, whereULMs are complete systems that can implement all possible logic functions utilizing the corresponding S/D expansions of many-valued Shannon and Davio spectral transforms.

Multi-Inputs/Outputs and Cascadable MEMS Resonator-Based Computing Devices

2020 ◽  
Author(s):  
Sherif A. Tella ◽  
Mohammad I. Younis
Keyword(s):  
Logic Gates ◽  
Vibrational Modes ◽  
Computational Power ◽  
Input Output ◽  
Practical Applications ◽  
Mems Resonator ◽  
Half Adder ◽  
Increasing Demand ◽  
Logic Functions ◽  
A Current

Abstract Due to the increasing demand for smarter solutions and embedded systems, MEMS resonator-based computing devices have been under considerable attention for their simplicity and prospect of low computational power. However, most complex logic functions require multi-input/output lines that are cascadable such that the outputs of one device can be used as inputs into subsequent devices for practical applications, and this is a current limitation for MEMS logic devices. In this study, we demonstrate multi-inputs/outputs half-adder function, AND, and XOR logic gates on the basis of activating and deactivating the localization and delocalization of the multi vibrational modes of a single MEMS resonator with improved energy efficiency.

scholarly journals Computation of Galois field expressions for quaternary logic functions on GPUs

2014 ◽  
Vol 11 (1) ◽  
pp. 97-109
Author(s):  
Dusan Gajic
Keyword(s):  
Graphics Processing Units ◽  
Digital Signal ◽  
Galois Field ◽  
Limiting Factor ◽  
Central Processing ◽  
Processing Times ◽  
Spectral Interpretation ◽  
Problem Instances ◽  
Logic Functions ◽  
Graphics Processing

Galois field (GF) expressions are polynomials used as representations of multiple-valued logic (MVL) functions. For this purpose, MVL functions are considered as functions defined over a finite (Galois) field of order p - GF(p). The problem of computing these functional expressions has an important role in areas such as digital signal processing and logic design. Time needed for computing GF-expressions increases exponentially with the number of variables in MVL functions and, as a result, it often represents a limiting factor in applications. This paper proposes a method for an accelerated computation of GF(4)-expressions for quaternary (four-valued) logic functions using graphics processing units (GPUs). The method is based on the spectral interpretation of GF-expressions, permitting the use of fast Fourier transform (FFT)-like algorithms for their computation. These algorithms are then adapted for highly parallel processing on GPUs. The performance of the proposed solutions is compared with referent C/C++ implementations of the same algorithms processed on central processing units (CPUs). Experimental results confirm that the presented approach leads to significant reduction in processing times (up to 10.86 times when compared to CPU processing). Therefore, the proposed approach widens the set of problem instances which can be efficiently handled in practice.

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