scholarly journals Performance analysis of a flexible polyimide based device for displacement sensing

2015 ◽  
Vol 28 (2) ◽  
pp. 287-296 ◽  
Author(s):  
Milica Kisic ◽  
Nelu Blaz ◽  
Kalman Babkovic ◽  
Andrea Maric ◽  
Goran Radosavljevic ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Circuit Board ◽  
Displacement Sensor ◽  
Heterogeneous Integration ◽  
Integration Process ◽  
Flexible Membrane ◽  
Printed Circuit ◽  
Internal Structures ◽  
Polyimide Foil ◽  
Simulation Results

In this work, two variations of the displacement sensor, based on the heterogeneous integration process of traditional fabrication technologies PCB (Printed Circuit Board) and LTCC (Low Temperature Co-fired Technology) with a flexible polyimide foil are presented. The proposed sensor uses the coil as an essential part, spacer and a polyimide foil as a flexible membrane with a piece of ferrite attached to it. With the displacement of the polyimide foil, the ferrite gets closer to the coil causing an increase in its inductance and a decrease of the resonant frequency of the system (coil, ferrite and antenna). Simulation results showed that sensors with equal outer dimensions but different internal structures exhibit different performances. Two prototypes of the sensor with different ferrite dimensions are designed, fabricated and characterized. Finally, their performances are compared.

scholarly journals Research on Small Square PCB Rogowski Coil Measuring Transient Current in the Power Electronics Devices

Sensors ◽  
2019 ◽  
Vol 19 (19) ◽  
pp. 4176 ◽  
Author(s):  
Chaoqun Jiao ◽  
Juan Zhang ◽  
Zhibin Zhao ◽  
Zuoming Zhang ◽  
Yuanliang Fan
Keyword(s):  
Power Electronics ◽  
Printed Circuit Board ◽  
Electronic Devices ◽  
Rogowski Coil ◽  
Bipolar Transistors ◽  
Circuit Board ◽  
Power Electronic ◽  
Insulated Gate Bipolar Transistors ◽  
Printed Circuit ◽  
Internal Structures

With the development of China’s electric power, power electronics devices such as insulated-gate bipolar transistors (IGBTs) have been widely used in the field of high voltages and large currents. However, the currents in these power electronic devices are transient. For example, the uneven currents and internal chip currents overshoot, which may occur when turning on and off, and could have a great impact on the device. In order to study the reliability of these power electronics devices, this paper proposes a miniature printed circuit board (PCB) Rogowski coil that measures the current of these power electronics devices without changing their internal structures, which provides a reference for the subsequent reliability of their designs.

Design, Materials, Process, and Fabrication of Fan-Out Panel-Level Heterogeneous Integration

2018 ◽  
Vol 15 (4) ◽  
pp. 141-147 ◽  
Author(s):  
Cheng-Ta Ko ◽  
Henry Yang ◽  
John Lau ◽  
Ming Li ◽  
Margie Li ◽  
...  
Keyword(s):  
Seed Layer ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Heterogeneous Integration ◽  
Assembly Process ◽  
Molding Compound ◽  
Printed Circuit ◽  
Chip Size ◽  
Design Materials ◽  
Dry Film

Abstract The design, materials, process, and fabrication of a heterogeneous integration of four chips by a fan-out panel-level packaging (FOPLP) method are investigated in this study. Emphasis is placed on (1) the application of a dry-film epoxy molding compound for molding the chips and (2) the application of a special assembly process called uni-substrate-integrated package for fabricating the redistribution layers (RDLs) of the FOPLP. The Ajinomoto build-up film is used as the dielectric of the RDLs and is built up by the semiadditive process. Electroless Cu is used to make the seed layer, laser direct imaging is used for opening the photoresist, and printed circuit board (PCB) Cu plating is used for making the conductor wiring of the RDLs. The panel dimensions are 508 × 508 mm. The package dimensions of the FOPLP are 10 × 10 mm. The large chip size and the small chip sizes are, respectively, 5 × 5 mm and 3 × 3 mm. The uniqueness of this study is that all the processes are carried out by using the PCB equipment.

Electrical Chip-Board Interaction (e-CBI) of Wafer Level Packaging Technology

2017 ◽  
Vol 2017 (1) ◽  
pp. 000325-000330 ◽  
Author(s):  
Wei Zhao ◽  
Mark Nakamoto ◽  
Karthikeyan Dhandapani ◽  
Brian Henderson ◽  
Ron Lindley ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Measured Data ◽  
Circuit Board ◽  
Wafer Level ◽  
Test Chip ◽  
Chip Design ◽  
Packaging Technology ◽  
Printed Circuit ◽  
Wafer Level Packaging ◽  
Simulation Results

Abstract Electrical Chip Board Interaction (e-CBI) has emerged as a new risk in chip design as silicon die can directly interact with printed circuit board (PCB) in substrate-less wafer level packaging technology. To assess this risk Qualcomm Technologies, Inc. has converted an existing test chip to wafer level packaging technology. Both the measured data and simulation results show that e-CBI risk is significant and must be carefully managed.

scholarly journals A Diffusor/Nozzle Pump Based on a Magnetically Actuated Flexible PCB Diaphragm

Proceedings ◽  
2018 ◽  
Vol 2 (13) ◽  
pp. 1077
Author(s):  
Marcus A. Hintermüller ◽  
Bernhard Jakoby
Keyword(s):  
Printed Circuit Board ◽  
Microfluidic Channel ◽  
Circuit Board ◽  
Fabrication Method ◽  
Flexible Membrane ◽  
Printed Circuit ◽  
Magnetically Actuated ◽  
Lorentz Forces ◽  
Out Of Plane ◽  
Flexible Printed Circuit

We present a valveless microfluidic pump utilizing an oscillating membrane made from a flexible printed circuit board. The microfluidic channel is fabricated by a 3D printing process and features diffuser/nozzle structures to obtain a directed flow; the flexible membrane is bonded to the channel. The membrane is actuated via Lorentz forces to accomplish out-of-plane motions and push the fluid through the channel. A permanent magnet provides the static magnetic field required for the actuation. The simple fabrication method can potentially be used for inexpensive mass fabrication for disposable devices.

Design, Materials, Process, and Fabrication of Fan-Out Panel-Level Heterogeneous Integration

2018 ◽  
Vol 2018 (1) ◽  
pp. 000057-000063 ◽  
Author(s):  
Cheng-Ta Ko ◽  
Henry Yang ◽  
John Lau ◽  
Ming Li ◽  
Margie Li ◽  
...  
Keyword(s):  
Seed Layer ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Heterogeneous Integration ◽  
Additive Process ◽  
Molding Compound ◽  
Printed Circuit ◽  
Chip Size ◽  
Design Materials ◽  
Dry Film

Abstract The design, materials, process, and fabrication of a heterogeneous integration of 4 chips by a FOPLP (fanout panel-level packaging) method are investigated in this study. Emphasis is placed on (a) the application of a dry-film EMC (epoxy molding compound) for molding the chips, and (b) the application of a special assembly process called Uni-SIP (uni-substrate-integrated-package) for fabricating the RDLs (redistribution layers) of the FOPLP. The ABF (Ajinomoto build-up film) is used as the dielectric of the RDLs and is built up by the SAP (semi-additive process). The electroless Cu is used to make the seed layer, the LDI (laser direct imaging) is used for opening the photoresist, and the PCB (printed circuit board) Cu plating is used for making the conductor wiring of the RDLs. The panel dimensions are 508mm × 508mm. The package dimensions of the FOPLP are 10mm × 10mm. The large chip size and the small chip sizes are, respectively 5mm × 5mm and 3mm × 3mm.

scholarly journals Chip-Last (RDL-First) Fan-Out Panel-Level Packaging (FOPLP) for Heterogeneous Integration

2020 ◽  
Vol 17 (3) ◽  
pp. 89-98
Author(s):  
John H. Lau ◽  
Cheng-Ta Ko ◽  
Chia-Yu Peng ◽  
Kai-Ming Yang ◽  
Tim Xia ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Printed Circuit Board ◽  
Drop Test ◽  
Circuit Board ◽  
Reliability Test ◽  
Heterogeneous Integration ◽  
Test Results ◽  
Glass Panel ◽  
Printed Circuit

Abstract In this investigation, the chip-last, redistribution-layer (RDL)–first, fan-out panel-level packaging (FOPLP) for heterogeneous integration is studied. Emphasis is placed on the materials, process, fabrication, and reliability of a heterogeneous integration of one large chip (10 × 10 mm2) and two small chips (7 × 5 mm2) by an FOPLP method on a 20 × 20-mm2 RDL-first substrate fabricated on a 515 × 510 mm2 temporary glass panel. Reliability test such as the drop test of the heterogeneous integration package on a printed circuit board (PCB) is performed, and test results including failure analysis are presented. Some recommendations are also provided.

scholarly journals Novel Dual band SIW Filter Using Quad mode Cavity

2019 ◽  
Vol 69 (5) ◽  
pp. 453-457
Author(s):  
Sambaiah Pelluri ◽  
Anmol Jain ◽  
M. V. Kartikeyan
Keyword(s):  
Printed Circuit Board ◽  
Single Layer ◽  
Circuit Board ◽  
Dual Band ◽  
Printed Circuit ◽  
Transmission Zeros ◽  
Measurement Results ◽  
Simulation Results ◽  
Filter Prototype ◽  
Insertion Losses

A dual-band bandpass substrate integrated waveguide (SIW) filter is proposed using a quad-mode cavity in this paper. First two degenerative modes (TE102 and TE201) with via perturbation give the first passband. The second passband is realised by using higher modes (side and diagonal modes of TE202) which are obtained by putting square slot at the center of the cavity. The square slot increases the frequency ratio of the center frequencies of first and second passbands. Moreover, orthogonal feed-lines are used in the proposed design to increase transmission zeros (TZs) which helps to improve the selectivity and out-of-band rejection of the filter. Designed and fabricated a dualband filter prototype using a single layer printed circuit board (PCB) technology, size is only 19 mm × 19 mm. The insertion losses are 2.1 dB and 2.4 dB, and fractional bandwidths of 3.40 per cent and 2.00 per cent at 11.00 and 15.58 GHz, respectively. The measurement results show close agreement with the simulation results.

scholarly journals Comparative Study of Crosstalk Reduction Techniques in RF Printed Circuit Board Using FDTD Method

2015 ◽  
Vol 2015 ◽  
pp. 1-9
Author(s):  
Rajeswari Packianathan ◽  
Raju Srinivasan
Keyword(s):  
High Speed ◽  
Printed Circuit Boards ◽  
Printed Circuit Board ◽  
Electromagnetic Coupling ◽  
Fdtd Method ◽  
Numerical Results ◽  
Circuit Board ◽  
Good Correspondence ◽  
Printed Circuit ◽  
Simulation Results

Miniaturization of the feature size in modern electronic circuits results from placing interconnections in close proximity with a high packing density. As a result, coupling between the adjacent lines has increased significantly, causing crosstalk to become an important concern in high-performance circuit design. In certain applications, microstriplines may be used in printed circuit boards for propagating high-speed signals, rather than striplines. Here, the electromagnetic coupling effects are analyzed for various microstrip transmission line structures, namely, microstriplines with a guard trace, double stub microstriplines, and parallel serpentine microstriplines using the finite-difference time-domain method. The numerical results are compared with simulation results, where the variants are simulated using an Ansoft high-frequency structure simulator. The analysis and simulation results are experimentally validated by fabricating a prototype and establishing a good correspondence between them. Numerical results are compared with simulation and experimental results, showing that double stub microstriplines reduce the far end crosstalk by 7 dB and increase the near end crosstalk by about 2 dB compared with the parallel microstriplines. Parallel serpentine microstriplines reduce the far end crosstalk by more than 10 dB and also reduce more than 15 mV of peak far end crosstalk voltage, compared with parallel microstriplines.

Chip-Last (RDL-First) Fan-Out Panel-Level Packaging (FOPLP) for Heterogeneous Integration

2020 ◽  
Vol 2020 (1) ◽  
pp. 000042-000050
Author(s):  
John H Lau ◽  
Cheng-Ta Ko ◽  
Chia-Yu Peng ◽  
Kai-Ming Yang ◽  
Tim Xia ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Printed Circuit Board ◽  
Drop Test ◽  
Circuit Board ◽  
Reliability Test ◽  
Heterogeneous Integration ◽  
Test Results ◽  
Glass Panel ◽  
Printed Circuit

Abstract In this investigation, the chip-last, RDL (redistribution-layer)-first, fan-out panel-level packaging (FOPLP) for heterogeneous integration is studied. Emphasis is placed on the materials, process, fabrication, and reliability of a heterogeneous integration of one large chip (10mm × 10mm) and two small chips (7mm × 5mm) by a FOPLP method on a 20mm × 20mm RDL-first substrate fabricated on a 515mm × 510mm temporary glass panel. Reliability test such as the drop test of the heterogeneous integration package on a PCB (printed circuit board) is performed and test results including failure analysis are presented. Some recommendations are also provided.

scholarly journals A wide bandwidth emitter for Ku band antenna array application

2019 ◽  
Vol 30 ◽  
pp. 05027
Author(s):  
Mikhail Snastin ◽  
Elena Dobychina
Keyword(s):  
Antenna Array ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Antenna Element ◽  
Wide Bandwidth ◽  
Printed Circuit ◽  
Simulation Results ◽  
Ku Band

The results of electrodynamic simulation of a wide bandwidth antenna emitter for Ku band are presented. The emitter in question has two orthogonal linear polarizations and is designed on multilayer printed circuit board. The simulation results of a four-element antenna array based on that antenna element are also presented.

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