scholarly journals Layout considerations for high temperature SRAM cells in a SOI technology

2003 ◽  
Vol 16 (2) ◽  
pp. 205-214
Author(s):  
Sonja Richter ◽  
Stefan Bormann ◽  
Valentin Nakov
Keyword(s):  
High Temperature ◽  
Random Access ◽  
Silicon On Insulator ◽  
Leakage Currents ◽  
Circuit Element ◽  
Memory Design ◽  
Advantages And Disadvantages ◽  
Low Leakage ◽  
Sram Cell ◽  
Soi Technology

Silicon-on-insulator technologies are well suited for high temperature circuit design, due to low leakage currents. The reduction of leakage currents is especially important in large repetitive structures such as memories. This paper describes the layout development of a high temperature SRAM cell in a SOI Technology. First, the differences between SOI technologies and standard CMOS processes are presented. It is then discussed, how SOI specific circuit element behavior affects the layout design of different parts of the SRAM cell. Solutions for SOI specific problems are presented and advantages and disadvantages of SOI technologies in static random access memory design are shown.

CNTFET-Based Memory Design

2020 ◽  
pp. 16-36
Author(s):  
Shashi Bala ◽  
Mamta Khosla ◽  
Raj Kumar
Keyword(s):  
Random Access ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Suitable Alternative ◽  
Memory Design ◽  
Noise Margin ◽  
Sram Cell ◽  
Static Power ◽  
Effect Transistor

As the feature size of device has been scaling down for many decades, conventional CMOS technology-based static random access memory (SRAM) has reached its limit due to significant leakage power. Therefore, carbon nanotube field effect transistor (CNTFET) can be considered most suitable alternative for SRAM. In this chapter, the performance and stability of CNTFET-based SRAM cells have been analyzed. Numerous figures of merit (FOM) (e.g., read/write noise margin, power dissipation, and read/write delay) have been considered to analyze the performance of CNTFET-based. The static power consumption in CNTFET-based SRAM cell was compared with conventional complementary metal oxide semiconductor (CMOS)-based SRAM cell. Conventional CNTFET and tunnel CNTFET-based SRAMs have also been considered for comparison. From the simulation results, it is observed that tunnel CNTFET SRAM cells have shown improved FOM over conventional CNTFET 6T SRAM cells without losing stability.

Conduction Uniformity Improvement of ESD Protection Device in 0.35 μm Partially-Depleted SOI Salicided CMOS Technology

2014 ◽  
Vol 687-691 ◽  
pp. 3251-3254
Author(s):  
Zhuo Tian ◽  
Bai Cheng Li
Keyword(s):  
Cmos Technology ◽  
Alpha Particles ◽  
Soft Error ◽  
Silicon On Insulator ◽  
Low Power Consumption ◽  
Protection Device ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Esd Protection ◽  
Soi Technology

ComparedtobulkCMOStechnology,Silicon-on-Insulator (SOI) CMOS technology has many advantages, such as low power consumption, low leakage current, low parasitic capacitance and a low soft error rate from both alpha particles and cosmic rays. However,electrostatic discharge (ESD) protection in SOI technology is still a major substantial barrier to overcome for the poor thermal conductivity of isolation oxide and the absence of vertical diode and silicon controlled rectifier (SCR).

Silicon-On-Insulator Mosfets Fabricated in Zone-Melting-Recrystallized Poly-Si Films on SiO2

1981 ◽  
Vol 4 ◽  
Author(s):  
B­Y. Tsaur ◽  
M. W. Gels ◽  
John C. C. Fan ◽  
D. J. Silversmith ◽  
R. W. Mountain
Keyword(s):  
Carrier Mobility ◽  
High Surface ◽  
Zone Melting ◽  
Silicon On Insulator ◽  
Surface Electron ◽  
Leakage Currents ◽  
Si Substrates ◽  
Enhancement Mode ◽  
Low Leakage ◽  
Si Films

ABSTRACTN- and p-channel enhancement-mode MOSFETs have been fabricated in Si films prepared by zone-melting recrystallization of poly-Si deposited on SiO2-coated Si substrates. The transistors exhibit high surface mobilities, in the range of 560–620 cm2/V−s for electrons and 200–240 cm2/V−s for holes, and low leakage currents of the order of 0.1 pA/μm (channel width). Uniform device performance with a yield exceeding 90% has been measured in tests of more than 100 devices. The interface between the Si film and the SiO2 layer on the substrate is characterized by an oxide charge density of 1–2 × 1011 cm−2 and a high surface carrier mobility. N-channel MOSFETs fabricated inSi films recrystallized on SiO2-coated fused quartz subtrates exhibit surface electron mobilities substantially higher than those of single-crystal Si devices because the films are under a large tensile stress.

scholarly journals Enhanced High Temperature Power Controller

2011 ◽  
Vol 2011 (HITEN) ◽  
pp. 000134-000138
Author(s):  
Joseph A. Henfling ◽  
Stan Atcitty ◽  
Frank Maldonado
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Integrated Circuits ◽  
Smart Grid ◽  
Implementation Strategy ◽  
Silicon On Insulator ◽  
The Other ◽  
Power Controller ◽  
Soi Technology

This paper describes an implementation strategy used to develop a high temperature power controller. The system is based on using high-temperature (HT) silicon-on-insulator (SOI) technology with silicon carbide (SiC) based integrated circuits (ICs) to create an efficient, high-temperature power controller. Two drives were tested with this system, one using normally off JFET switching and the other using MOSFET switching. Normally off JFETs made from SiC were used to drive the output loads. Such circuit designs will improve the efficiency of future smart grid power controllers.

scholarly journals A new circuit technique for reduced leakage current in Deep Submicron CMOS technologies

2005 ◽  
Vol 3 ◽  
pp. 355-358
Author(s):  
A. Schmitz ◽  
R. Tielert
Keyword(s):  
Supply Voltage ◽  
Logic Gate ◽  
Deep Submicron ◽  
Soft Error ◽  
Sleep Mode ◽  
Leakage Currents ◽  
Low Leakage ◽  
Sram Cell ◽  
Local Supply ◽  
Standby Mode

Abstract. Modern CMOS processes in the Deep Submicron regime are restricted to supply voltages below 2 volts and further to account for the transistors' field strength limitations and to reduce the power per logic gate. To maintain the high switching performance, the threshold voltage must be scaled according with the supply voltage. However, this leads to an increased subthreshold current of the transistors in standby mode (VGS=0). Another source of leakage is gate current, which becomes significant for gate oxides of 3nm and below. We propose a Self-Biasing Virtual Rails (SBVR) - CMOS technique which acts like an adaptive local supply voltage in case of standby mode. Most important sources of leakage currents are reduced by this technique. Moreover, SBVR-CMOS is capable of conserving stored information in sleep mode, which is vital for memory circuits. Memories are exposed to radiation causing soft errors. This well-known problem becomes even worse in standby mode of typical SRAMs, that have low driving performance to withstand alpha particle hits. In this paper, a 16-transistor SRAM cell is proposed, which combines the advantage of extremely low leakage currents with a very high soft error stability.

An Ultra-Low Noise Instrumentation Amplifer Designed for High Temperature Applications

2012 ◽  
Vol 2012 (HITEC) ◽  
pp. 000082-000086
Author(s):  
Jeff Watson ◽  
Gustavo Castro
Keyword(s):  
High Temperature ◽  
High Performance ◽  
Low Noise ◽  
Silicon On Insulator ◽  
Instrumentation Amplifier ◽  
Leakage Currents ◽  
Comprehensive Reliability ◽  
High Temperature Operation ◽  
Temperature Applications

This paper discusses a very low noise instrumentation amplifier designed specifically for high temperature applications. The device uses a proprietary silicon-on-insulator process that minimizes parasitic leakage currents at elevated temperature. Variance in device parameters are managed to maintain high performance over a wide temperature range. Layout and packaging considerations that would affect long term reliability are addressed. The amplifier is well characterized above 200°C and attains much higher performance than amplifiers not optimized for high temperature operation. Comprehensive reliability testing over temperature has been completed.

scholarly journals Design, Implementation and Analysis of 8T SRAM Cell in Memory Array

2018 ◽  
Vol 7 (3.1) ◽  
pp. 101
Author(s):  
B Kaleeswari ◽  
S Kaja Mohideen
Keyword(s):  
Leakage Current ◽  
Power Analysis ◽  
High Performance ◽  
Random Access ◽  
Vital Role ◽  
Access Memory ◽  
Memory Design ◽  
Design Structure ◽  
Sram Cell ◽  
Scale Down

In modern VLSI designs, static random access memory plays a vital role because of its high performance and low power consumption qualities. As technology is scale down, the importance of the power analysis and leakage current of memory design is increasing. This paper describes about the 1 KB size memory design using SRAM. The proposed design of 8T SRAM single cell in implemented in array structure of size 32x32.The design structure reduces the power by 75% by reducing the leakage current. The proposed 8T SRAM cell is implemented and analyzed in 90nm technology using Digital schematic and Micro wind software. 

scholarly journals A Novel Approach to Design SRAM Cells for Low Leakage and Improved Stability

2018 ◽  
Vol 8 (4) ◽  
pp. 41 ◽  
Author(s):  
Tripti Tripathi ◽  
Durg Chauhan ◽  
Sanjay Singh
Keyword(s):  
High Speed ◽  
Random Access ◽  
Memory Cell ◽  
Handheld Devices ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Novel Approach ◽  
Prime Concern ◽  
Sram Cell ◽  
Improved Stability

The semiconductor electronic industry is advancing at a very fast pace. The size of portable and handheld devices are shrinking day by day and the demand for longer battery backup is also increasing. With these requirements, the leakage power in stand-by mode becomes a critical concern for researchers. In most of these devices, memory is an integral part and its size also scales down as the device size is reduced. So, low power and high speed memory design is a prime concern. Another crucial factor is the stability of static random-access memory (SRAM) cells. This paper combines multi threshold and fingering techniques to propose a modified 6T SRAM cell which has high speed, improved stability and low leakage current in stand-by mode of the memory cell. The simulations are done using the Cadence Virtuoso tool on UMC 55 nm technology.

scholarly journals A Low Leakage 9T SRAM Cell With Improve Stability in Sub-Threshold Region for IoT Applications

2021 ◽  
Author(s):  
Harekrishna Kumar ◽  
V.K Tomar
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Random Access ◽  
Mean Value ◽  
Access Time ◽  
Threshold Region ◽  
Low Leakage ◽  
Noise Margin ◽  
Sram Cell ◽  
Forward Body Bias

Abstract This paper presents a single-ended read and differential write half select free 9T static random access memory (SRAM) cell operates in the sub-threshold region. Proposed 9T SRAM cell shows a reasonable reduction in read and write power dissipation by a factor of 1.41× and 2.1× respectively as of conventional 6T (Conv.6T) SRAM cell. The stacking of transistors at core latch network minimizes the leakage power of the cell. The read static noise margin (RSNM) and write margin (WM) are upgraded by 2.16× and 2.06× respectively as of Conv.6T cell. A forward body bias technique is utilized in read path which results to decreases in read access time by a factor of 2.72× as of standard 6T SRAM cell. The mean value of Ion/Ioff ratio of the proposed cell is improved by 2.92× as compared to the Conv.6T SRAM cell. It is attributed to a reduction in bit-line leakage current. To achieve more soundness in characteristics of the proposed 9T SRAM cell, process variation effect on RSNM, power dissipation, and read current is calculated through Monte Carlo (MC) simulation at 5000 points. The obtained results are compared with reference SRAM cells at 0.3V supply voltage.

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