scholarly journals Extracting PCB components based on color distribution of highlight areas

2010 ◽  
Vol 7 (1) ◽  
pp. 13-30 ◽  
Author(s):  
Zhou Zeng ◽  
Zhuang Li ◽  
Zuoyong Zheng
Keyword(s):  
Solder Joint ◽  
Protective Coating ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Color Distribution ◽  
Printed Circuit ◽  
Distribution Features ◽  
Via Holes ◽  
Two Stages

This paper investigates methodologies for locating and identifying the components on a printed circuit board (PCB) used for surface mount device inspection. The proposed scheme consists of two stages: solder joint extraction and protective coating extraction. Solder joints are extracted by first detecting all the highlight areas, and then recognizing and removing the invalid highlight areas which are mainly markings and via-holes. We sum up three color distribution features. And the invalid highlight areas are recognized and removed by comparing the features of the target objects and the reference objects. The sequence of color distribution as a new clue has been applied to clustering solder joints. Each protective coating is extracted by the positions of the clustered solder joints. Experimental results show that the proposed method can extract most of components effectively.

scholarly journals The Effect of Epoxy Polymer Addition in Sn-Ag-Cu and Sn-Bi Solder Joints

Materials ◽  
2019 ◽  
Vol 12 (6) ◽  
pp. 960 ◽  
Author(s):  
Min-Soo Kang ◽  
Do-Seok Kim ◽  
Young-Eui Shin
Keyword(s):  
Solder Joint ◽  
Strain Energy ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Solder Paste ◽  
Element Analysis ◽  
Printed Circuit ◽  
Shock Testing ◽  
Polymer Addition

To analyze the reinforcement effect of adding polymer to solder paste, epoxies were mixed with two currently available Sn-3.0Ag-0.5Cu (wt.% SAC305) and Sn-59Bi (wt.%) solder pastes and specimens prepared by bonding chip resistors to a printed circuit board. The effect of repetitive thermal stress on the solder joints was then analyzed experimentally using thermal shock testing (−40 °C to 125 °C) over 2000 cycles. The viscoplastic stress–strain curves generated in the solder were simulated using finite element analysis, and the hysteresis loop was calculated. The growth and propagation of cracks in the solder were also predicted using strain energy formulas. It was confirmed that the epoxy paste dispersed the stress inside the solder joint by externally supporting the solder fillet, and crack formation was suppressed, improving the lifetime of the solder joint.

Materials Characterization of Lead Free Compositions for Minimum Temperature SMT Processes at the SLI-Second Level Interconnect Solder Joint

2004 ◽  
Author(s):  
Norman J. Armendariz ◽  
Prawin Paulraj
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Gold Surface ◽  
Circuit Board ◽  
Lead Free ◽  
Processing Temperature ◽  
The European Union ◽  
Printed Circuit ◽  
Higher Temperature ◽  
Tin Silver Copper

Abstract The European Union is banning the use of Pb in electronic products starting July 1st, 2006. Printed circuit board assemblies or “motherboards” require that planned CPU sockets and BGA chipsets use lead-free solder ball compositions at the second level interconnections (SLI) to attach to a printed circuit board (PCB) and survive various assembly and reliability test conditions for end-use deployment. Intel is pro-actively preparing for this anticipated Pb ban, by evaluating a new lead free (LF) solder alloy in the ternary Tin- Silver-Copper (Sn4.0Ag0.5Cu) system and developing higher temperature board assembly processes. This will be pursued with a focus on achieving the lowest process temperature required to avoid deleterious higher temperature effects and still achieve a metallurgically compatible solder joint. One primary factor is the elevated peak reflow temperature required for surface mount technology (SMT) LF assembly, which is approximately 250 °C compared to present eutectic tin/lead (Sn37Pb) reflow temperatures of around 220 °C. In addition, extended SMT time-above-liquidus (TAL) and subsequent cooling rates are also a concern not only for the critical BGA chipsets and CPU BGA sockets but to other components similarly attached to the same PCB substrate. PCBs used were conventional FR-4 substrates with organic solder preservative on the copper pads and mechanical daisychanged FCBGA components with direct immersion gold surface finish on their copper pads. However, a materials analysis method and approach is also required to characterize and evaluate the effect of low peak temperature LF SMT processing on the PBA SLI to identify the absolute limits or “cliffs” and determine if the minimum processing temperature and TAL could be further lowered. The SLI system is characterized using various microanalytical techniques, such as, conventional optical microscopy, scanning electron microscopy, energy dispersive spectroscopy and microhardness testing. In addition, the SLI is further characterized using macroanalytical techniques such as dye penetrant testing (DPT) with controlled tensile testing for mechanical strength in addition to disbond and crack area mapping to complete the analysis.

Experimental Investigation by Speckle Interferometry of Solder Joint Failure Under Thermomechanical Load Aggravated by Boundary Conditions at Board Level

2012 ◽  
Vol 134 (4) ◽  
Author(s):  
D. N. Borza ◽  
I. T. Nistea
Keyword(s):  
Solder Joint ◽  
Fundamental Frequency ◽  
Printed Circuit Board ◽  
Speckle Interferometry ◽  
Circuit Board ◽  
Joint Failure ◽  
Printed Circuit ◽  
Out Of Plane ◽  
Fringe Patterns ◽  
Board Level

Reliability of electronic assemblies at board level and solder joint integrity depend upon the stress applied to the assembly. The stress is often of thermomechanical or of vibrational nature. In both cases, the behavior of the assembly is strongly influenced by the mechanical boundary conditions created by the printed circuit board (PCB) to casing fasteners. In many previously published papers, the conditions imposed to the fasteners are mostly aiming at an increase of the fundamental frequency and a decrease of static or dynamic displacement values characterizing the deformation. These conditions aim at reducing the fatigue in different parts of these assemblies. In the photomechanics laboratory of INSA Rouen, the origins of solder joint failure have been investigated by means of full-field measurements of the flexure deformation induced by vibrations or by forced thermal convection. The measurements were done both at a global level for the whole printed circuit board assembly (PCBA) and at a local level at the solder joints where failure was reported. The experimental technique used was phase-stepped laser speckle interferometry. This technique has a submicrometer sensitivity with respect to out-of-plane deformations induced by bending and its use is completely nonintrusive. Some of the results were comforted by comparison with a numerical finite elements model. The experimental results are presented either as time-average holographic fringe patterns, as in the case of vibrations, or as wrapped phase patterns, as in the case of deformation under thermomechanical stress. Both types of fringe patterns may be processed so as to obtain the explicit out-of-plane static deformation (or vibration amplitude) maps. Experimental results show that the direct cause of solder joint failure may be a high local PCB curvature produced by a supplementary fastening screw intended to reduce displacements and increase fundamental frequency. The curvature is directly responsible for tensile stress appearing in the leads of a large quad flat pack (QFP) component and for shear in the corresponding solder joints. The general principle of increasing the fundamental frequency and decreasing the static or dynamic displacement values has to be checked against the consequences on the PCB curvature near large electronic devices having high stiffness.

Numerical Model to Simulate the Drop Test of Printed Circuit Board (PCB)

2011 ◽  
Vol 423 ◽  
pp. 26-30
Author(s):  
S. Assif ◽  
M. Agouzoul ◽  
A. El Hami ◽  
O. Bendaou ◽  
Y. Gbati
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Drop Test ◽  
Dynamic Responses ◽  
Circuit Board ◽  
Joint Stress ◽  
Printed Circuit ◽  
Increasing Demand ◽  
Improved Model ◽  
Board Level

Increasing demand for smaller consumer electronic devices with multi-function capabilities has driven the packaging architectures trends for the finer-pitch interconnects, thus increasing chances of their failures. A simulation of the Board Level Drop-Test according to JEDEC (Joint Electron Device Council) is performed to evaluate the solder joint reliability under drop impact test. After good insights to the physics of the problem, the results of the numerical analysis on a simple Euler-Bernoulli beam were validated against analytical analysis. Since the simulation has to be performed on ANSYS Mechanical which is an implicit software, two methods were proposed, the acceleration-input and the displacement-input. The results are the same for both methods. Therefore, the simulation is carried on the real standard model construction of the board package level2. Then a new improved model is proposed to satisfy shape regular element and accuracy. All the models are validated to show excellent first level correlation on the dynamic responses of Printed Circuit Board, and second level correlation on solder joint stress. Then a static model useful for quick design analysis and optimization’s works is proposed and validated. Finally, plasticity behavior is introduced on the solder ball and a non-linear analysis is performed.

Pretreatment of Blind Via Holes before Ni/Au and Cu Plating Applied with Atmospheric Pressure Plasma Jet

2005 ◽  
Vol 2 (3) ◽  
pp. 189-196 ◽  
Author(s):  
Yasushi Sawada ◽  
Keiichi Yamazaki ◽  
Noriyuki Taguchi ◽  
Tetsuji Shibata
Keyword(s):  
Atmospheric Pressure ◽  
Printed Circuit Board ◽  
Formation Rate ◽  
Plasma Processing ◽  
Atmospheric Pressure Plasma ◽  
Plasma Jet ◽  
Circuit Board ◽  
Bottom Surface ◽  
Printed Circuit ◽  
Via Holes

The effectiveness of atmospheric pressure (AP) plasma preprocessing before Ni/Au or Cu plating has been examined by applying it to a build-up printed circuit board (FR-4 grade) and polyimide-based flexible circuit film, both with blind via-holes (BVHs). The AP plasma applied with a dielectric barrier discharge is generated inside a 56 mm wide quartz vessel by an RF power generator using Ar-O2 gas mixture. One side of the vessel is open and the plasma jet is blown on the sample substrate transported 5 mm downward from the outlet of the vessel. The deposit failure rate of Ni/Au electroless deposit to 50 μm-diameter BVHs formed on a photo resist on the printed circuit board is 12.5% without preprocessing but is decreased to 0% after applying the AP plasma processing. As for 50 μm-diameter BVHs formed with a YAG laser on a polyimide-based flexible circuit film, the bump formation using electrolytic copper plating fails without preprocessing, but a 100% bump formation rate is achieved after applying AP plasma processing. It is presumed that the AP plasma processing improves the wetting property of the BVH walls and allows the plating solution to uniformly cover the entire wall surfaces without generating bubbles. The removal of organic substances attached to the BVH bottom surface also helps to improve the adherence of metal plating.

High-Speed Cyclic Bend Tests and Board-Level Drop Tests for Evaluating the Robustness of Solder Joints in Printed Circuit Board Assemblies

2009 ◽  
Vol 38 (6) ◽  
pp. 884-895 ◽  
Author(s):  
E.H. Wong ◽  
S.K.W. Seah ◽  
C.S. Selvanayagam ◽  
R. Rajoo ◽  
W.D. van Driel ◽  
...  
Keyword(s):  
High Speed ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Printed Circuit ◽  
Drop Tests ◽  
Bend Tests ◽  
Board Level
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