scholarly journals A 2.56 GHz Radiation Hard Phase Locked Loop ASIC for High Speed Serial Communication Links

2018 ◽  
Author(s):  
Jeffrey Prinzie ◽  
Michiel Steyaert ◽  
Paulo Moreira ◽  
Paul Leroux
2021 ◽  
Author(s):  
Sameh Soliman

The current high-growth nature of digital communications demands higher speed serial communication circuits. Present day technologies barely manage to keep up with this demand, and new techniques are required to ensure that serial communication can continnue to expand and grow. The goal of this work is to optimize the performance of an essential building block of serial communication circuits, namely, the phase-locked loop (PLL), so that it can cope with today's high-speed communication. Due to its popularity, the optimization has targeted the charge-pump-based implementqation of the phase-locked loop. This goal is achieved by researching, designing, and evaluating high speed serial communication circuits. Research has involved an in-depth study of the state of the art in high-speed serial communication circuits ; high-speed, controlled oscillators, and CMOS technology. An LC, voltage-controlled oscillator (VCO) is designed in 0.18-micron, mixed-signal, 6-metal-2-poly, CMOS process. A novel tuning technique is employed to tune its output frequency. Simulation results shows that it provides quadrature and differential outputs, operates with 10 GHz center frequency, 600-MHz tuning range centered around its center frequency, and phase noise of -95 dBc/Hz at 1-MHz offset from the fundamental harmonic of its output, and draws 10 ,A of DC current from a single 1.8-V power supply. Also, it exhibits a good linearity throughout its tuning range. The new tuning technique increases the tuning range of the VCO to 6% of its center frequency compared to the 1-to-2% typical value. As its locking performance depends on the characteristic of the employed VCO and to demonstrate the effect of optimizing the tuning range of the VCO, a charge-pump PLL is designed. Simulation results shows that the PLL acquisition range is 300 MHz compared to a maximum value of 100 MHz when a conventional LC VCO is employed. Also, as a measure of its tracking range, the maximum frequency slew rate of its input has improved by 40%.


2003 ◽  
Vol 47 (2.3) ◽  
pp. 259-282 ◽  
Author(s):  
D. J. Friedman ◽  
M. Meghelli ◽  
B. D. Parker ◽  
J. Yang ◽  
H. A. Ainspan ◽  
...  

2021 ◽  
Author(s):  
Sameh Soliman

The current high-growth nature of digital communications demands higher speed serial communication circuits. Present day technologies barely manage to keep up with this demand, and new techniques are required to ensure that serial communication can continnue to expand and grow. The goal of this work is to optimize the performance of an essential building block of serial communication circuits, namely, the phase-locked loop (PLL), so that it can cope with today's high-speed communication. Due to its popularity, the optimization has targeted the charge-pump-based implementqation of the phase-locked loop. This goal is achieved by researching, designing, and evaluating high speed serial communication circuits. Research has involved an in-depth study of the state of the art in high-speed serial communication circuits ; high-speed, controlled oscillators, and CMOS technology. An LC, voltage-controlled oscillator (VCO) is designed in 0.18-micron, mixed-signal, 6-metal-2-poly, CMOS process. A novel tuning technique is employed to tune its output frequency. Simulation results shows that it provides quadrature and differential outputs, operates with 10 GHz center frequency, 600-MHz tuning range centered around its center frequency, and phase noise of -95 dBc/Hz at 1-MHz offset from the fundamental harmonic of its output, and draws 10 ,A of DC current from a single 1.8-V power supply. Also, it exhibits a good linearity throughout its tuning range. The new tuning technique increases the tuning range of the VCO to 6% of its center frequency compared to the 1-to-2% typical value. As its locking performance depends on the characteristic of the employed VCO and to demonstrate the effect of optimizing the tuning range of the VCO, a charge-pump PLL is designed. Simulation results shows that the PLL acquisition range is 300 MHz compared to a maximum value of 100 MHz when a conventional LC VCO is employed. Also, as a measure of its tracking range, the maximum frequency slew rate of its input has improved by 40%.


2018 ◽  
Vol 65 (1) ◽  
pp. 407-412 ◽  
Author(s):  
Jeffrey Prinzie ◽  
Jorgen Christiansen ◽  
Paulo Moreira ◽  
Michiel Steyaert ◽  
Paul Leroux

2019 ◽  
Vol 0 (0) ◽  
Author(s):  
Festus Idowu Oluwajobi ◽  
Nguyen Dong-Nhat ◽  
Amin Malekmohammadi

AbstractIn this paper, the performance of a novel multilevel signaling based on Manchester code namely four-level Manchester Coding (4-MC) technique is investigated for next generation high-speed optical fiber communication links. The performance of 4-MC is studied and compared with conventional Manchester modulation and four-level pulse amplitude modulation (4-PAM) formats in terms of receiver sensitivity, spectral efficiency and dispersion tolerance at the bit rate of 40 Gb/s. The bit error rate (BER) calculation model for the proposed multilevel scheme has also been developed. The calculated receiver sensitivity and the chromatic dispersion tolerance at the BER of 10–9 of the proposed scheme are −22 dBm and 67.5 ps/nm, respectively. It is observed that, 4-MC scheme is superior in comparison to 4-PAM by 3.5 dB in terms of receiver sensitivity in back-to-back scenario. Therefore, the proposed scheme can be considered as an alternative to current 4-PAM system.


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