scholarly journals URANIUM-BISMUTH IN-PILE CORROSION TEST LOOP. RADIATION LOOP NO. 1

1961 ◽  
Author(s):  
C.H. Waide ◽  
L.E. Kukacka ◽  
R.A. Meyer ◽  
J. Milau ◽  
J.H. Klein ◽  
...  
Author(s):  
Alebachew Demoz ◽  
Kirk H. Michaelian ◽  
John Donini ◽  
Sankara Papavinasam ◽  
R. Winston Revie

A multi-purpose instrumented loop in line with an oil producing well is described. The loop has several ports for coupons which were replaced periodically. Some of the coupons were used for electrochemical monitoring in addition to weight loss and visual inspection. Weight loss, pit rate and all the electrochemical methods used gave corrosion rates that were dependent on the positions of the coupons inside the loop. The corrosion rate of the coupons increased from top to bottom. This order reflected the media and flow to which the coupons were exposed in a multi-phase producing well.


2008 ◽  
pp. 36-36-12 ◽  
Author(s):  
T-L Yau ◽  
RT Webster
Keyword(s):  

1991 ◽  
Vol 36 (1-2) ◽  
pp. 175-194 ◽  
Author(s):  
R. E. Pawel ◽  
G. L. Yoder ◽  
D. K. Felde ◽  
B. H. Montgomery ◽  
M. T. McFee

Author(s):  
Chungho Cho ◽  
Woonkyu Lee ◽  
Choonho Cho ◽  
Jongman Kim ◽  
Tae Yung Song

Lead corrosion test loop named KPAL-II (KAERI Pb Alloy Loop II) has been designed and fabricated at the Korea Atomic Energy Research Institute (KAERI) and an initial operation was performed recently. The KPAL-II was designed to study the long-term corrosive effects of liquid lead on structural and fuel cladding materials at temperatures up to 600°C. The first run of KPAL-II took place on March 15th, 2006 and three hundred hours of shakedown testing were performed with an isothermal condition at about 450°C. This paper summarizes the general design concept and the results of the shakedown testing of KPAL-II.


Author(s):  
Rudolf Schlangen ◽  
Jon Colburn ◽  
Joe Sarmiento ◽  
Bala Tarun Nelapatla ◽  
Puneet Gupta

Abstract Driven by the need for higher test-compression, increasingly many chip-makers are adopting new DFT architectures such as “Extreme-Compression” (XTR, supported by Synopsys) with on-chip pattern generation and MISR based compression of chain output data. This paper discusses test-loop requirements in general and gives Advantest 93k specific guidelines on test-pattern release and ATE setup necessary to enable the most established EFA techniques such as LVP and SDL (aka DLS, LADA) within the XTR test architecture.


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