scholarly journals Czochralski growth of gallium indium antimonide alloy crystals

1998 ◽  
Author(s):  
S.C. Tsaur
1957 ◽  
Vol 35 (1) ◽  
pp. 91-97 ◽  
Author(s):  
J. S. Blakemore

Electrical conductivity and Hall effect are measured for p-type specimens of polycrystalline GaSb.InSb with impurity concentration about 1017 cm.−3. Analysis of these data suggests that μn/μp = 11, and that the intrinsic gap varies linearly with temperature from 0.265 ev. at 0° K. Measurement of the photoconductive limit at various temperatures shows that the gap widens on heating, though the electrical data seem difficult to reconcile with the large gradient of +1.1 × 10−3 ev./°C. indicated by the optical data.


Author(s):  
C.M. Sung ◽  
M. Levinson ◽  
M. Tabasky ◽  
K. Ostreicher ◽  
B.M. Ditchek

Directionally solidified Si/TaSi2 eutectic composites for the development of electronic devices (e.g. photodiodes and field-emission cathodes) were made using a Czochralski growth technique. High quality epitaxial growth of silicon on the eutectic composite substrates requires a clean silicon substrate surface prior to the growth process. Hence a preepitaxial surface cleaning step is highly desirable. The purpose of this paper is to investigate the effect of surface cleaning methods on the epilayer/substrate interface and the characterization of silicon epilayers grown on Si/TaSi2 substrates by TEM.Wafers were cut normal to the <111> growth axis of the silicon matrix from an approximately 1 cm diameter Si/TaSi2 composite boule. Four pre-treatments were employed to remove native oxide and other contaminants: 1) No treatment, 2) HF only; 3) HC1 only; and 4) both HF and HCl. The cross-sectional specimens for TEM study were prepared by cutting the bulk sample into sheets perpendicular to the TaSi2 fiber axes. The material was then prepared in the usual manner to produce samples having a thickness of 10μm. The final step was ion milling in Ar+ until breakthrough occurred. The TEM samples were then analyzed at 120 keV using the Philips EM400T.


2018 ◽  
Vol 1 (1) ◽  
pp. 78-94
Author(s):  
I. A. Obukhov ◽  
◽  
G. G. Gorokh ◽  
A. A. Lozovenko ◽  
E. A. Smirnova ◽  
...  
Keyword(s):  

2015 ◽  
Vol 9 (1) ◽  
pp. 170-174 ◽  
Author(s):  
Xiaoling Zhang ◽  
Qingduan Meng ◽  
Liwen Zhang

The square checkerboard buckling deformation appearing in indium antimonide infrared focal-plane arrays (InSb IRFPAs) subjected to the thermal shock tests, results in the fracturing of the InSb chip, which restricts its final yield. In light of the proposed three-dimensional modeling, we proposed the method of thinning a silicon readout integrated circuit (ROIC) to level the uneven top surface of InSb IRFPAs. Simulation results show that when the silicon ROIC is thinned from 300 μm to 20 μm, the maximal displacement in the InSb IRFPAs linearly decreases from 7.115 μm to 0.670 μm in the upward direction, and also decreases linearly from 14.013 μm to 1.612 μm in the downward direction. Once the thickness of the silicon ROIC is less than 50 μm, the square checkerboard buckling deformation distribution presenting in the thicker InSb IRFPAs disappears, and the top surface of the InSb IRFPAs becomes flat. All these findings imply that the thickness of the silicon ROIC determines the degree of deformation in the InSb IRFPAs under a thermal shock test, that the method of thinning a silicon ROIC is suitable for decreasing the fracture probability of the InSb chip, and that this approach improves the reliability of InSb IRFPAs.


1977 ◽  
Vol 42 ◽  
pp. 503-506 ◽  
Author(s):  
Th. Hangleiter ◽  
J.M. Spaeth

Sign in / Sign up

Export Citation Format

Share Document