scholarly journals High-Level Modeling and Simulation of a Novel Reconfigurable Network-on-Chip Router

2015 ◽  
Vol 4 (3-4) ◽  
Author(s):  
Thanh-Vu Le-Van ◽  
Xuan-Tu Tran
Keyword(s):  
Network Architecture ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Communication Mode ◽  
Router Architecture ◽  
High Level Modeling ◽  
Network Platform ◽  
On Chip ◽  
High Level ◽  
Network Router

In this paper, we present a novel router architecture for implementing a Reconfigurable Network-on-Chip (RNoC) at high-level design using SystemC. The RNoC is an adaptive NoC-based system-on-chip providing a dynamic reconfigurable communication mechanism. By adding a virtual port – named Routing Modification port – into the conventional router architecture, the network router is able to route communication data flexibly whenever the target routing path is blocked, by unwanted defects or intently by a software programme to meet the requirements of applications. The proposed architecture has been modeled in SystemC/C++, simulated and verified within a 2D mesh 5×5 network platform. In normal communication mode, the static XY routing algorithm is used while the West-First algorithm with a proposed prohibited router surrounding technique is applied in reconfiguration mode. Experimental results are also reported to compare the performance of the network architecture in different operation modes as well as with other works.

scholarly journals NoCGuard: A Reliable Network-on-Chip Router Architecture

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 342 ◽  
Author(s):  
Muhammad Akmal Shafique ◽  
Naveed Khan Baloch ◽  
Muhammad Iram Baig ◽  
Fawad Hussain ◽  
Yousaf Bin Zikria ◽  
...  
Keyword(s):  
Network Architecture ◽  
Fault Tolerant ◽  
Channel Allocation ◽  
High Reliability ◽  
Low Cost ◽  
Network On Chip ◽  
Time To Failure ◽  
Protection Factor ◽  
Router Architecture ◽  
On Chip

Aggressive scaling in deep nanometer technology enables chip multiprocessor design facilitated by the communication-centric architecture provided by Network-on-Chip (NoC). At the same time, it brings considerable challenges in reliability because a fault in the network architecture severely impacts the performance of a system. To deal with these reliability challenges, this research proposed NoCGuard, a reconfigurable architecture designed to tolerate multiple permanent faults in each pipeline stage of the generic router. NoCGuard router architecture uses four highly reliable and low-cost fault-tolerant strategies. We exploited resource borrowing and double routing strategy for the routing computation stage, default winner strategy for the virtual channel allocation stage, runtime arbiter selection and default winner strategy for the switch allocation stage and multiple secondary bypass paths strategy for the crossbar stage. Unlike existing reliable router architectures, our architecture features less redundancy, more fault tolerance, and high reliability. Reliability comparison using Mean Time to Failure (MTTF) metric shows 5.53-time improvement in a lifetime and using Silicon Protection Factor (SPF), 22-time improvement, which is better than state-of-the-art reliable router architectures. Synthesis results using 15 nm and 45 nm technology library show that additional circuitry incurs an area overhead of 28.7% and 28% respectively. Latency analysis using synthetic, PARSEC and SPLASH-2 traffic shows minor increase in performance by 3.41%, 12% and 15% respectively while providing high reliability.

Pre-allocated Path Based Low Latency Router Architecture for Network-on-chip

2014 ◽  
Vol 35 (2) ◽  
pp. 341-346
Author(s):  
Xiao-fu Zheng ◽  
Hua-xi Gu ◽  
Yin-tang Yang ◽  
Zhong-fan Huang
Keyword(s):  
Network On Chip ◽  
Low Latency ◽  
Router Architecture ◽  
On Chip

scholarly journals Load-balanced routing algorithm for Network-on-Chip employing fair arbiter

2021 ◽  
Vol 1871 (1) ◽  
pp. 012117
Author(s):  
Lu Liu ◽  
Yanfei Yang ◽  
Qianqian Lei ◽  
Huhu Wang ◽  
Song Lixun
Keyword(s):  
Routing Algorithm ◽  
Network On Chip ◽  
On Chip ◽  
Load Balanced

A Novel Adaptive Routing Algorithm for Network-On-Chip

2011 ◽  
Vol 474-476 ◽  
pp. 413-416
Author(s):  
Jia Jia ◽  
Duan Zhou ◽  
Jian Xian Zhang
Keyword(s):  
Routing Algorithm ◽  
Adaptive Routing ◽  
Network On Chip ◽  
Experimental Results ◽  
Average Latency ◽  
On Chip

In this paper, we propose a novel adaptive routing algorithm to solve the communication congestion problem for Network-on-Chip (NoC). The strategy competing for output ports in both X and Y directions is employed to utilize the output ports of the router sufficiently, and to reduce the transmission latency and improve the throughput. Experimental results show that the proposed algorithm is very effective in relieving the communication congestion, and a reduction in average latency by 45.7% and an improvement in throughput by 44.4% are achieved compared with the deterministic XY routing algorithm and the simple XY adaptive routing algorithm.

Design of Router Supporting Multiply Routing Algorithm for NoC

2014 ◽  
Vol 981 ◽  
pp. 431-434
Author(s):  
Zhan Peng Jiang ◽  
Rui Xu ◽  
Chang Chun Dong ◽  
Lin Hai Cui
Keyword(s):  
Complex System ◽  
High Performance ◽  
Routing Algorithm ◽  
Network On Chip ◽  
System On Chip ◽  
Low Latency ◽  
Deterministic Routing ◽  
Key Features ◽  
Design Challenge ◽  
On Chip

Network on Chip(NoC)，a new proposed solution to solve global communication problem in complex System on Chip (SoC) design，has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus，and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

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