Routing Algorithm for Application-Specific Network-on-Chip with Irregular Core Sizes

In this paper, we propose a novel adaptive routing algorithm to solve the communication congestion problem for Network-on-Chip (NoC). The strategy competing for output ports in both X and Y directions is employed to utilize the output ports of the router sufficiently, and to reduce the transmission latency and improve the throughput. Experimental results show that the proposed algorithm is very effective in relieving the communication congestion, and a reduction in average latency by 45.7% and an improvement in throughput by 44.4% are achieved compared with the deterministic XY routing algorithm and the simple XY adaptive routing algorithm.

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Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures

2010 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2010.60 ◽

2010 ◽

Cited By ~ 2

Author(s):

Iasonas Filippopoulos ◽

Iraklis Anagnostopoulos ◽

Alexandros Bartzas ◽

Dimitrios Soudris ◽

George Economakos

Keyword(s):

Energy Efficient ◽

Network On Chip ◽

Systematic Exploration ◽

On Chip ◽

Application Specific

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Application-specific 3D Network-on-Chip design using simulated allocation

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) ◽

10.1109/aspdac.2010.5419830 ◽

2010 ◽

Cited By ~ 4

Author(s):

Pingqiang Zhou ◽

Ping-Hung Yuh ◽

Sachin S. Sapatnekar

Keyword(s):

Network On Chip ◽

Chip Design ◽

3D Network ◽

On Chip ◽

Application Specific

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Design of Router Supporting Multiply Routing Algorithm for NoC

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.981.431 ◽

2014 ◽

Vol 981 ◽

pp. 431-434

Author(s):

Zhan Peng Jiang ◽

Rui Xu ◽

Chang Chun Dong ◽

Lin Hai Cui

Keyword(s):

Complex System ◽

High Performance ◽

Routing Algorithm ◽

Network On Chip ◽

System On Chip ◽

Low Latency ◽

Deterministic Routing ◽

Key Features ◽

Design Challenge ◽

On Chip

Network on Chip(NoC)，a new proposed solution to solve global communication problem in complex System on Chip (SoC) design，has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus，and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

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