Identification of Research Gaps in an Efficient Designing of Application Specific Instruction Set Processor (ASIP) for Neural Prosthetics

2019 ◽  
Author(s):  
Naresh Kumar Janwa ◽  
Dr. Manoj Kumar Jain
Keyword(s):  
Instruction Set ◽  
Research Gaps ◽  
Specific Instruction ◽  
Neural Prosthetics ◽  
Application Specific

An Application Specific Instruction Set Processor (ASIP) for Adaptive Filters in Neural Prosthetics

2015 ◽  
Vol 12 (5) ◽  
pp. 1034-1047 ◽  
Author(s):  
Yao Xin ◽  
Will X.Y. Li ◽  
Zhaorui Zhang ◽  
Ray C.C. Cheung ◽  
Dong Song ◽  
...  
Keyword(s):  
Adaptive Filters ◽  
Instruction Set ◽  
Specific Instruction ◽  
Neural Prosthetics ◽  
Application Specific

Efficient Computing in Image Processing and DSPs with ASIP Based Multiplier

2019 ◽  
Vol 13 (2) ◽  
pp. 174-180
Author(s):  
Poonam Sharma ◽  
Ashwani Kumar Dubey ◽  
Ayush Goyal
Keyword(s):  
Image Processing ◽  
High Speed ◽  
Computation Time ◽  
Digital Signal ◽  
Instruction Set ◽  
Computationally Efficient ◽  
Specific Instruction ◽  
Processor Core ◽  
Speed Performance ◽  
Application Specific

Background: With the growing demand of image processing and the use of Digital Signal Processors (DSP), the efficiency of the Multipliers and Accumulators has become a bottleneck to get through. We revised a few patents on an Application Specific Instruction Set Processor (ASIP), where the design considerations are proposed for application-specific computing in an efficient way to enhance the throughput. Objective: The study aims to develop and analyze a computationally efficient method to optimize the speed performance of MAC. Methods: The work presented here proposes the design of an Application Specific Instruction Set Processor, exploiting a Multiplier Accumulator integrated as the dedicated hardware. This MAC is optimized for high-speed performance and is the application-specific part of the processor; here it can be the DSP block of an image processor while a 16-bit Reduced Instruction Set Computer (RISC) processor core gives the flexibility to the design for any computing. The design was emulated on a Xilinx Field Programmable Gate Array (FPGA) and tested for various real-time computing. Results: The synthesis of the hardware logic on FPGA tools gave the operating frequencies of the legacy methods and the proposed method, the simulation of the logic verified the functionality. Conclusion: With the proposed method, a significant improvement of 16% increase in throughput has been observed for 256 steps iterations of multiplier and accumulators on an 8-bit sample data. Such an improvement can help in reducing the computation time in many digital signal processing applications where multiplication and addition are done iteratively.

Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors

2017 ◽  
Vol 66 (4) ◽  
pp. 647-660 ◽  
Author(s):  
Tuo Li ◽  
Muhammad Shafique ◽  
Jude Angelo Ambrose ◽  
Jorg Henkel ◽  
Sri Parameswaran
Keyword(s):  
Instruction Set ◽  
Specific Instruction ◽  
Fine Grained ◽  
Checkpoint Recovery ◽  
Instruction Set Processors ◽  
Application Specific
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