State of the Art of Integrated Circuits

1964 ◽  
Author(s):  
J. R. Buyan
Keyword(s):  
Integrated Circuits ◽  
State Of The Art

Test and Diagnosis of Automotive Embedded Processors via High-Speed Standard Interfaces

2017 ◽  
Vol 26 (08) ◽  
pp. 1740006
Author(s):  
Christian Gleichner ◽  
Heinrich T. Vierhaus
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
System Reliability ◽  
High Speed ◽  
State Of The Art ◽  
Fault Analysis ◽  
Production Test ◽  
System Failure ◽  
Functional Tests ◽  
The Embedded System

In state-of-the-art automotive controllers, functional tests are used to check their integrity in the field. Features dedicated to production test of integrated circuits such as scan chains are not applied in the embedded system. However, such test structures enable a more effective and diagnostic test, which improves the fault analysis in case of a system failure and even increases system reliability. To achieve this, an access to the integrated test logic is required. This paper describes a concept of a test access to embedded systems via high-speed standard interfaces. The extended test logic as well as an appropriate test routine is presented.

scholarly journals Recent Progress in Silicon Photonics: A Review

ISRN Optics ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-27 ◽  
Author(s):  
Zhou Fang ◽  
Ce Zhou Zhao
Keyword(s):  
Integrated Circuits ◽  
Silicon Photonics ◽  
Recent Progress ◽  
State Of The Art ◽  
Low Cost ◽  
Photonic Integrated Circuits ◽  
High Data ◽  
Bandwidth Requirement ◽  
Rate Transmission ◽  
Data Rate Transmission

With the increasing bandwidth requirement in computing and signal processing, the inherent limitations in metallic interconnection are seriously threatening the future of traditional IC industry. Silicon photonics can provide a low-cost approach to overcome the bottleneck of the high data rate transmission by replacing the original electronic integrated circuits with photonic integrated circuits. Although the commercial promise has not been realized, this perspective gives huge impetus to the development of silicon photonics these years. This paper provides an overview of the progress and the state of the art of each component in silicon photonics, including waveguides, filters, modulators, detectors, and lasers, mainly in the last five years.

scholarly journals Ultra-fast germanium photodiode with 3-dB bandwidth of 265 GHz

2021 ◽  
Author(s):  
S. Lischke ◽  
A. Peczek ◽  
J. S. Morgan ◽  
K. Sun ◽  
D. Steckler ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
State Of The Art ◽  
Photonic Integrated Circuits ◽  
Bandwidth Efficiency ◽  
Novel Device ◽  
Silicon Devices ◽  
Performance Specifications ◽  
Dark Currents

AbstractOn a scalable silicon technology platform, we demonstrate photodetectors matching or even surpassing state-of-the-art III–V devices. As key components in high-speed optoelectronics, photodetectors with bandwidths greater than 100 GHz have been a topic of intense research for several decades. Solely InP-based detectors could satisfy the highest performance specifications. Devices based on other materials, such as germanium-on-silicon devices, used to lag behind in speed, but enabled complex photonic integrated circuits and co-integration with silicon electronics. Here we demonstrate waveguide-coupled germanium photodiodes with optoelectrical 3-dB bandwidths of 265 GHz and 240 GHz at a photocurrent of 1 mA. This outstanding performance is achieved by a novel device concept in which a germanium fin is sandwiched between complementary in situ-doped silicon layers. Our photodetectors show internal responsivities of 0.3 A W−1 (265 GHz) and 0.45 A W−1 (240 GHz) at a wavelength of 1,550 nm. The internal bandwidth–efficiency product of the latter device is 86 GHz. Low dark currents of 100–200 nA are obtained from these ultra-fast photodetectors.

scholarly journals Integrated ARM big.Little-Mali Pipeline for High-Throughput CNN Inference

2021 ◽  
Author(s):  
Ehsan Aghapour ◽  
A. Pathania ◽  
Gayathri Ananthanarayanan
Keyword(s):  
Integrated Circuits ◽  
High Throughput ◽  
Computer Aided Design ◽  
Heterogeneous System ◽  
State Of The Art ◽  
Embedded Platform ◽  
Computer Aided ◽  
On Chip ◽  
Aided Design ◽  
Pipeline Design

<div>State-of-the-art Heterogeneous System on Chips (HMPSoCs) can perform on-chip embedded inference on its CPU and GPU. Multi-component pipelining is the method of choice to provide high-throughput Convolutions Neural Network (CNN) inference on embedded platforms. In this work, we provide details for the first CPU-GPU pipeline design for CNN inference called Pipe-All. Pipe-All uses the ARM-CL library to integrate an ARM big.Little CPU with an ARM Mali GPU. Pipe-All is the first three-stage CNN inference pipeline design with ARM’s big CPU cluster, Little CPU cluster, and Mali GPU as its stages. Pipe-All provides on average 75.88% improvement in inference throughput (over peak single-component inference) on Amlogic A311D HMPSoC in Khadas Vim 3 embedded platform. We also provide an open-source implementation for Pipe-All.</div><div>This paper is submitted to IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) as a transaction brief paper (5 pages).</div>

scholarly journals State-of-the-Art and Perspectives on Silicon Waveguide Crossings: A Review

Micromachines ◽  
2020 ◽  
Vol 11 (3) ◽  
pp. 326 ◽  
Author(s):  
Sailong Wu ◽  
Xin Mu ◽  
Lirong Cheng ◽  
Simei Mao ◽  
H.Y. Fu
Keyword(s):  
Integrated Circuits ◽  
State Of The Art ◽  
Design Method ◽  
Photonic Devices ◽  
Research Directions ◽  
Subwavelength Grating ◽  
Silicon Waveguide ◽  
Mode Division Multiplexing ◽  
Silicon Photonic ◽  
Inverse Design Method

In the past few decades, silicon photonics has witnessed a ramp-up of investment in both research and industry. As a basic building block, silicon waveguide crossing is inevitable for dense silicon photonic integrated circuits and efficient crossing designs will greatly improve the performance of photonic devices with multiple crossings. In this paper, we focus on the state-of-the-art and perspectives on silicon waveguide crossings. It reviews several classical structures in silicon waveguide crossing design, such as shaped taper, multimode interference, subwavelength grating, holey subwavelength grating and vertical directional coupler by forward or inverse design method. In addition, we introduce some emerging research directions in crossing design including polarization-division-multiplexing and mode-division-multiplexing technologies.

scholarly journals A Preconditioned Iterative Approach for Efficient Full Chip Thermal Analysis on Massively Parallel Platforms

Technologies ◽  
2018 ◽  
Vol 7 (1) ◽  
pp. 1
Author(s):  
George Floros ◽  
Konstantis Daloukas ◽  
Nestor Evmorfopoulos ◽  
George Stamoulis
Keyword(s):  
Integrated Circuits ◽  
Iterative Method ◽  
State Of The Art ◽  
Massively Parallel ◽  
Computationally Efficient ◽  
Linear Solvers ◽  
Massively Parallel Architectures ◽  
3D Integrated Circuits ◽  
Preconditioned Iterative ◽  
Formulation Problem

Efficient full-chip thermal simulation is among the most challenging problems facing the EDA industry today, especially for modern 3D integrated circuits, due to the huge linear systems resulting from thermal modeling approaches that require unreasonably long computational times. While the formulation problem, by applying a thermal equivalent circuit, is prevalent and can be easily constructed, the corresponding 3D equations network has an undesirable time-consuming numerical simulation. Direct linear solvers are not capable of handling such huge problems, and iterative methods are the only feasible approach. In this paper, we propose a computationally-efficient iterative method with a parallel preconditioned technique that exploits the resources of massively-parallel architectures such as Graphic Processor Units (GPUs). Experimental results demonstrate that the proposed method achieves a speedup of 2.2× in CPU execution and a 26.93× speedup in GPU execution over the state-of-the-art iterative method.

scholarly journals Hardware Trojans in Chips: A Survey for Detection and Prevention

Sensors ◽  
2020 ◽  
Vol 20 (18) ◽  
pp. 5165
Author(s):  
Chen Dong ◽  
Yi Xu ◽  
Ximeng Liu ◽  
Fan Zhang ◽  
Guorong He ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
State Of The Art ◽  
Academic Community ◽  
The State ◽  
Third Party ◽  
Hardware Trojans ◽  
Advantages And Disadvantages ◽  
Wide Range ◽  
Ip Cores ◽  
Comprehensive Classification

Diverse and wide-range applications of integrated circuits (ICs) and the development of Cyber Physical System (CPS), more and more third-party manufacturers are involved in the manufacturing of ICs. Unfortunately, like software, hardware can also be subjected to malicious attacks. Untrusted outsourced manufacturing tools and intellectual property (IP) cores may bring enormous risks from highly integrated. Attributed to this manufacturing model, the malicious circuits (known as Hardware Trojans, HTs) can be implanted during the most designing and manufacturing stages of the ICs, causing a change of functionality, leakage of information, even a denial of services (DoS), and so on. In this paper, a survey of HTs is presented, which shows the threatens of chips, and the state-of-the-art preventing and detecting techniques. Starting from the introduction of HT structures, the recent researches in the academic community about HTs is compiled and comprehensive classification of HTs is proposed. The state-of-the-art HT protection techniques with their advantages and disadvantages are further analyzed. Finally, the development trends in hardware security are highlighted.

scholarly journals Module Based Floorplanning Methodology to Satisfy Voltage Island and Fixed Outline Constraints

Electronics ◽  
2018 ◽  
Vol 7 (11) ◽  
pp. 325 ◽  
Author(s):  
Srinath Balasubramanian ◽  
Arunapriya Panchanathan ◽  
Bharatiraja Chokkalingam ◽  
Sanjeevikumar Padmanaban ◽  
Zbigniew Leonowicz
Keyword(s):  
Integrated Circuits ◽  
Supply Voltage ◽  
State Of The Art ◽  
Power Reduction ◽  
Significant Rise ◽  
Tree Representation ◽  
Voltage Level ◽  
Island Constraints ◽  
Functional Blocks ◽  
Representation Scheme

Multiple supply voltage is the most prevalent method for low power reduction in the design of modern Integrated circuits. Floorplanning process in this design performs positioning of functional blocks in the layout satisfying both fixed outline and voltage island constraints. The floorplans while satisfying these two significant constraints causes significant rise in wirelength and congestion. In this paper, a congestion and wirelength aware floorplanning algorithm is proposed which allows effective placement of functional blocks in the layout to satisfying fixed outline and voltage island constraints simultaneously. To perform voltage island floorplanning, the proposed algorithm uses Skewed binary tree representation scheme to operate the functional blocks in its predefined voltage level. The proposed methodology determines the feasible dimensions of the functional blocks in the representation which aids the placement process for the reduction of congestion and wirelength. With these optimal dimensions of the functional blocks, floorplanning is also performed for the layouts of aspect 1:1, 2:1, and 3:1, to evaluate the ability of proposed algorithm for satisfying the fixed outline constraint. The proposed methodology is implemented in the layout of InternationalWorkshop on Logic and Synthesis (IWLS) benchmarks circuits for experimental purpose. The resulting floorplans were iteratively optimized for optimal reduction of wirelength and congestion. Experimental results show that the proposed methodology outperforms existing state-of-the-art approaches in wirelength reduction by about 18.65% and in congestion reduction by around 63%, while delivering the 30.35% power consumption.

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