Special Issue on Computer Architecture for Robotics

1990 ◽  
Vol 2 (6) ◽  
pp. 417-417
Author(s):  
Michitaka Kameyama ◽  
Keyword(s):  
Computer Architecture ◽  
Integrated Circuit ◽  
High Speed ◽  
High Performance ◽  
System Development ◽  
General Purpose ◽  
System Configuration ◽  
Design Development ◽  
Very High ◽  
Vlsi Chips

In the realization of intelligent robots, highly intelligent manipulation and movement techniques are required such as intelligent man-machine interfaces, intelligent information processing for path planning and problem solutions, practical robot vision, and high-speed sensor signal processing. Thus, very high-speed processing to cope with vast amounts of data as well as the development of various algorithms has become important subjects. To fulfill such requirements, the development of high-performance computer architecture using advanced microelectronics technology is required. For these purposes, the development of implementing computer systems’ for robots will be classified as follows: (a) Use of general-purpose computers As the performance of workstations and personal computers is increased year by year, software development is the major task without requiring hardware development except the interfaces with peripheral equipment. Since current high-level languages and software can be applied, the approach is excellent in case of system development, but the processing performance is limited. (b) Use of commercially available (V) LSI chips This is an approach to design a computer system by the combination of commercially available LSIs. Since the development of both hardware and software is involved in this system development, the development period tends to be longer than in (a). These chips include general-purpose microprocessors, memory chips, digital signal processors (DSPs) and multiply-adder LSIs. Though the kinds of available chips are limited to some degree, the approach can cope with a considerably high-performance specifications because a number of chips can be flexibly used. (c) Design, development and system configuration of VLSI chips This is an approach to develop new special-purpose VLSI chips using ASIC (Application Specific Integrated Circuit) technology, that is, semicustom or full-custom technology. If these attain practical use and are marketed, they will be widely used as high-performance VLSI chips of the level (b). Since a very high-performance specification must be satisfied, the study of very high performance VLSI computer architecture becomes very important. But this approach involving chip development requires a very long period in the design-development from the determination of processor specifications to the system configuration using the fabricated chips. For the above three approaches, the order from the viewpoint of ease of development will be (a), (b) and (c), while that from the viewpoint of performance will be (c), (b) and (a). Each approach is not exclusive but is complementary each other. For example, the development of new chips by (c) can also give new impact as the components of (a) and (b). Further, the common point of these approaches is that performance improvement by highly parallel architecture becomes important. This special edition introduces, from the above standpoint, the latest information on the present state and' future prospects of the computer techniques in Japan. We hope that this edition will contribute to the development of this field.

scholarly journals SYNTHESIS AND FPGA–IMPLEMENTATION BASED NEURAL TECHNIQUE OF A NONLINEAR ADC MODEL

2014 ◽  
pp. 27-33
Author(s):  
Mounir Bouhedda ◽  
Mokhtar Attari
Keyword(s):  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Description Language ◽  
Description Language ◽  
Analog To Digital ◽  
Field Programmable ◽  
Hardware Description ◽  
Nonlinear Analog ◽  
Very High

The aim of this paper is to introduce a new architecture using Artificial Neural Networks (ANN) in designing a 6-bit nonlinear Analog to Digital Converter (ADC). A study was conducted to synthesise an optimal ANN in view to FPGA (Field Programmable Gate Array) implementation using Very High-speed Integrated Circuit Hardware Description Language (VHDL). Simulation and tests results are carried out to show the efficiency of the designed ANN.

High-Performance Reconfigurable Computing

2019 ◽  
pp. 731-744
Author(s):  
Mário Pereira Vestias
Keyword(s):  
Power Consumption ◽  
Integrated Circuit ◽  
Reconfigurable Computing ◽  
High Performance ◽  
General Purpose ◽  
Reconfigurable Hardware ◽  
Coarse Grained ◽  
Lower Power ◽  
Fine Grained ◽  
Application Specific

High-performance reconfigurable computing systems integrate reconfigurable technology in the computing architecture to improve performance. Besides performance, reconfigurable hardware devices also achieve lower power consumption compared to general-purpose processors. Better performance and lower power consumption could be achieved using application-specific integrated circuit (ASIC) technology. However, ASICs are not reconfigurable, turning them application specific. Reconfigurable logic becomes a major advantage when hardware flexibility permits to speed up whatever the application with the same hardware module. The first and most common devices utilized for reconfigurable computing are fine-grained FPGAs with a large hardware flexibility. To reduce the performance and area overhead associated with the reconfigurability, coarse-grained reconfigurable solutions has been proposed as a way to achieve better performance and lower power consumption. In this chapter, the authors provide a description of reconfigurable hardware for high-performance computing.

High-Performance Reconfigurable Computing

2018 ◽  
pp. 4018-4029
Author(s):  
Mário Pereira Vestias
Keyword(s):  
Power Consumption ◽  
Integrated Circuit ◽  
Reconfigurable Computing ◽  
High Performance ◽  
General Purpose ◽  
Reconfigurable Hardware ◽  
Coarse Grained ◽  
Lower Power ◽  
Fine Grained ◽  
Application Specific

High-Performance Reconfigurable Computing systems integrate reconfigurable technology in the computing architecture to improve performance. Besides performance, reconfigurable hardware devices also achieve lower power consumption compared to General-Purpose Processors. Better performance and lower power consumption could be achieved using Application Specific Integrated Circuit (ASIC) technology. However, ASICs are not reconfigurable, turning them application specific. Reconfigurable logic becomes a major advantage when hardware flexibility permits to speed up whatever the application with the same hardware module. The first and most common devices utilized for reconfigurable computing are fine-grained FPGAs with a large hardware flexibility. To reduce the performance and area overhead associated with the reconfigurability, coarse-grained reconfigurable solutions has been proposed as a way to achieve better performance and lower power consumption. In this chapter we will provide a description of reconfigurable hardware for high performance computing.

4H-SIC Dmosfets for High Frequency Power Switching Applications

2003 ◽  
Vol 764 ◽  
Author(s):  
Sei-Hyung Ryu ◽  
Anant K. Agarwal ◽  
James Richmond ◽  
John W. Palmour
Keyword(s):  
High Voltage ◽  
High Speed ◽  
High Performance ◽  
High Frequency Power ◽  
Power Devices ◽  
Power Switching ◽  
High Speed Switching ◽  
Unipolar Devices ◽  
Very High ◽  
Frequency Power

AbstractVery high critical field, reasonable bulk electron mobility, and high thermal conductivity make 4H-Silicon carbide very attractive for high voltage power devices. These advantages make high performance unipolar switching devices with blocking voltages greater than 1 kV possible in 4H-SiC. Several exploratory devices, such as vertical MOSFETs and JFETs, have been reported in SiC. However, most of the previous works were focused on high voltage aspects of the devices, and the high speed switching aspects of the SiC unipolar devices were largely neglected. In this paper, we report on the static and dynamic characteristics of our 4H-SiC DMOSFETs. A simple model of the on-state characteristics of 4H-SiC DMOSFETs is also presented.

CMOS INTEGRATED CIRCUIT CONTROLLERS FOR SWITCHING POWER CONVERTERS

2004 ◽  
Vol 13 (04) ◽  
pp. 789-811
Author(s):  
EDUARD ALARCÓN ◽  
GERARD VILLAR ◽  
ALBERTO POVEDA
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
High Performance ◽  
Power Converters ◽  
Correct Operation ◽  
Case Examples ◽  
Cmos Integrated Circuit ◽  
Switching Power ◽  
Switching Power Converters ◽  
On Chip

Two case examples of high-speed CMOS microelectronic implementations of high-performance controllers for switching power converters are presented. The design and implementation of a current-programmed controller and a general-purpose feedforward one-cycle controller are described. The integrated circuit controllers attain high-performance by means of using current-mode analog signal processing, hence allowing high switching frequencies that extend the operation margin compared to previous designs. Global layout-extracted transistor-level simulation results for 0.8 μm and 0.35 μm standard CMOS technologies confirm both the correct operation of the circuits in terms of bandwidth as well as their functionality for the control of switching power converters. The circuits may be used either as standalone IC controllers or as controller circuits that are technology-compatible with on-chip switching power converters and on-chip loads for future powered systems-on-chip.

III-V HETEROJUNCTION BIPOLAR TRANSISTORS FOR HIGH-SPEED APPLICATIONS

1990 ◽  
Vol 01 (03n04) ◽  
pp. 245-301 ◽  
Author(s):  
M.F. CHANG ◽  
P.M. ASBECK
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
High Speed ◽  
High Performance ◽  
Growth Parameters ◽  
Bipolar Transistors ◽  
System Requirements ◽  
Potential Impact ◽  
Computational Systems ◽  
Very High

Recent advances in communication, radar and computational systems demand very high performance electronic circuits. Heterojunction bipolar transistors (HBTs) have the potential of providing a more efficient solution to many key system requirements through intrinsic device advantages than competing technologies. This paper reviews the present status of GaAs and InP-based HBT technologies and their applications to digital, analog, microwave and multifunction circuits. It begins with a brief review of HBT device concepts and critical epitaxial growth parameters. Issues important for device modeling and fabrication technologies are discussed. The paper then highlights the performance and the potential impact of HBT devices and integrated circuits in various application areas. Key prospects for future HBT development are also addressed.

Integrated Optoelectronic Devices on Silicon

2012 ◽  
Vol 1396 ◽  
Author(s):  
Di Liang ◽  
John E. Bowers
Keyword(s):  
Output Power ◽  
Integrated Circuit ◽  
High Speed ◽  
High Performance ◽  
Continuous Wave ◽  
Light Emission ◽  
Extinction Ratio ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Pockels Effect

ABSTRACTSilicon (Si) has been the dominating material platform of microelectronics over half century. Continuous technological advances in circuit design and manufacturing enable complementary metal-oxide semiconductor (CMOS) chips with increasingly high integration complexity to be fabricated in an unprecedently scale and economical manner. Conventional Si-based planar lightwave circuits (PLCs) has benefited from advanced CMOS technology but only demonstrate passive functionalities in most circumstances due to poor light emission efficiency and weak major electro-optic effects (e.g., Pockels effect, the Kerr effect and the Franz–Keldysh effect) in Si. Recently, a new hybrid III-V-on-Si integration platform has been developed, aiming to bridge the gap between Si and III-V direct-bandgap materials for active Si photonic integrated circuit applications. Since then high-performance lasers, amplifiers, photodetectors and modulators, etc. have been demonstrated. Here we review the most recent progress on hybrid Si lasers and high-speed hybrid Si modulators. The former include distributed feedback (DFB) lasers showing over 10 mW output power and up to 85 oC continuous-wave (cw) operation, compact hybrid microring lasers with cw threshold less than 4 mA and over 3 mW output power, and 4-channel hybrid Si AWG lasers with channel space of 360 GHz. Recently fabricated traveling-wave electro-absorption modulators (EAMs) and Mach-Zehnder interferometer modulators (MZM) on this platform support 50 Gb/s and 40 Gb/s data transmission with over 10 dB extinction ratio, respectively.

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