A three-quarter watt seismic station

1972 ◽  
Vol 62 (4) ◽  
pp. 985-990 ◽  
Author(s):  
K. J. Muirhead ◽  
D. W. Simpson
Keyword(s):  
Dynamic Range ◽  
Seismic Station ◽  
Low Cost ◽  
Seismic Signal ◽  
Total Power ◽  
Time Signal ◽  
Direct Recording ◽  
Total Power Consumption ◽  
Seismic Recording ◽  
Crystal Clock

Abstract A low-power, low-cost instrument using slow speed, direct recording on magnetic tape provides continuous unattended seismic recording in excess of 1 month. The seismic signal is recorded at two gain levels separated by 26 db with a total dynamic range of greater than 70 db. A high-accuracy crystal clock with fully coded digital output and a crystal stabilized radio for reference time-signal reception provide timing to better than 0.1 sec throughout the recording period. Total power consumption is less than 34 watts which enables operation for 1 month on dry cell batteries. The weight of the complete system including seismometer and batteries is less than 100 lb. Ten instruments have been used to record seismic signals ranging from localized microearthquake activity to explosions and teleseismic events.

LOW COST, LOW POWER DIGITAL OPTICAL RECEIVER MODULE FOR 50 Mb/s PASSIVE OPTICAL NETWORK

1996 ◽  
Vol 07 (04) ◽  
pp. 471-489 ◽  
Author(s):  
YUSUKE OTA ◽  
ROBERT G. SWARTZ ◽  
JOHN S. SCHAFER ◽  
MIHAI M. BANU ◽  
ALFRED E. DUNLOP ◽  
...  
Keyword(s):  
Optical Networks ◽  
Dynamic Range ◽  
Low Cost ◽  
Optical Receiver ◽  
Passive Optical Network ◽  
Total Power ◽  
Printed Wiring Board ◽  
Plastic Package ◽  
Total Power Consumption ◽  
Receiver Module

A low cost digital optical receiver module for passive optical networks was developed. In order to reduce the cost of the receiver module, ICs are packaged in low cost plastic packages and the receiver module is fabricated using conventional surface mount technology. The receiver module is capable of receiving burst and packet digital optical signals, and recovered data and recovered clock in CMOS logic level are available. The receiver module contains a connectorized InGaAs PIN photodiode, a burst/packet mode-compatible preamplifier IC in a 32-lead TQFP plastic package, a comparator IC in an 8-lead SOIC plastic package, a clock recovery IC in a 32-lead TQFP plastic package and other active and passive components. These components are mounted on a four-layer printed wiring board. The intrinsic minimum receivable optical signal power is around -42 dBm/Ave and the dynamic range is over 26 dB for BER 1 × 10-8 at a bit rate of up to 60 Mb/s. The total power consumption of this module is less than 200 mW.

A CMOS Image Sensor with a Novel Passive Pixel Array and High Precision Current Amplifier for a Compact Digital X-ray Detector

2020 ◽  
Vol 10 (11) ◽  
pp. 2745-2753
Author(s):  
Jimin Cheon ◽  
Dongmyung Lee ◽  
Hojong Choi
Keyword(s):  
High Precision ◽  
Dynamic Range ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Total Power ◽  
Cmos Process ◽  
Current Amplifier ◽  
X Ray ◽  
Total Power Consumption ◽  
Pixel Array

An active pixel sensor (APS) in a digital X-ray detector is the dominant circuitry for a CMOS image sensor (CIS) despite its lower fill factor (FF) compared to that of a passive pixel sensor (PPS). Although the PPS provides higher FF, its overall signal-to-noise ratio (SNR) is lower than that of the APS. The required high resolution and small focal plane can be achieved by reducing the number of transistors and contacts per pixel. We proposed a novel passive pixel array and a high precision current amplifier to improve the dynamic range (DR) without minimizing the sensitivity for diagnostic compact digital X-ray detector applications. The PPS can be an alternative to improve the FF. However, size reduction of the feedback capacitor causes degradation of SNR performance. This paper proposes a novel PPS based on readout and amplification circuits with a high precision current amplifier to minimize performance degradation. The expected result was attained with a 0.35-μm CMOS process parameter with power supply voltage of 3.3 V. The proposed PPS has a saturation signal of 1.5 V, dynamic range of 63.5 dB, and total power consumption of 13.47 mW. Therefore, the proposed PPS readout circuit improves the dynamic range without sacrificing the sensitivity.

A Miniature Double Oscillating-Fan Cooling System Using Electromagnetic Force

2015 ◽  
Author(s):  
Hsien-Chin Su
Keyword(s):  
Electromagnetic Force ◽  
Structural Reliability ◽  
Cooling System ◽  
Low Cost ◽  
Total Power ◽  
Cooling Device ◽  
Design Flexibility ◽  
Total Power Consumption ◽  
Cooling Devices ◽  
Fan Cooling

In this study, an oscillating-fan cooling device using electromagnetic force has been proposed. The device consists of two oscillating-fans flapping back and forth. It requires only one electromagnet and two elastic blades with one magnet on each of them. The electromagnet and two elastic blades are situated on a base and arranged accordingly. And thus, the electromagnetic force generated by the electromagnet can actuate the blades. The main advantage of this cooling device compared to a rotary fan is its simple structure because there is no bearing and motor in the cooling device. Moreover, the simplicity of the device makes it a highly reliable and low cost cooling device. The driving current can be either DC PWM or AC under 8 V – 12 V so it is compatible to most electronic devices. The dimensions of the cooling device can be designed as small as 20 mm (L) * 30 mm (W) * 4 mm (H) and as large as 60 mm * 55 mm * 25 mm. For a cooling experiment, three cooling devices with the dimension of 50 mm * 50 mm * 15 mm were incorporated with a heat sink with the dimension of 190 mm * 110 mm * 15 m. The dummy heater dissipated 55W while the environmental temperature is 44.8 °C. The result showed that the dummy heater can be cooled from 120.7 °C to 69.3 °C while the total power consumption of the three cooling devices is 1.74 W. The result shows that the cooling device not only provides an outstanding cooling ability but also shows a great potential for structural reliability and design flexibility.

A cost-effective extracorporeal magnetically-levitated centrifugal blood pump employing a disposable magnet-free impeller

2011 ◽  
Vol 225 (12) ◽  
pp. 1149-1157 ◽  
Author(s):  
W Hijikata ◽  
T Mamiya ◽  
T Shinshi ◽  
S Takatani
Keyword(s):  
Degrees Of Freedom ◽  
Low Cost ◽  
Cost Effective ◽  
Magnetic Bearing ◽  
Blood Pump ◽  
Total Power ◽  
Centrifugal Blood Pump ◽  
Total Power Consumption ◽  
Pump Head ◽  
Rotary Blood Pumps

In the field of rotary blood pumps, contactless support of the impeller by a magnetic bearing has been identified as a promising method to reduce blood damage and enhance durability. The authors developed a two-degrees-of-freedom radial controlled magnetic bearing system without a permanent magnet in the impeller in order that a low-cost disposable pump-head for an extracorporeal centrifugal blood pump could be manufactured more easily. Stable levitation and contactless rotation of the ‘magnet-free’ impeller were realized for a prototype blood-pump that made use of this magnetic bearing. The run-out of the impeller position at between 1000 r/min and 3000 r/min was less than 40 µm in the radial-controlled directions. The total power consumption of the magnetic bearing was less than 1 W at the same rotational speeds. When the pump was operated, a flow rate of 5 l/min against a head pressure of 78.66 kPa was achieved at a rotational speed of 4000 r/min, which is sufficient for extracorporeal circulation support. The proposed technology offers the advantage of low-cost mass production of disposable pump heads.

Design of Low Power and High Precision Successive Approximation Register Analog-to-Digital Converter (SAR-ADC) Based on Piecewise Capacitance and Calibration Technique

2020 ◽  
Vol 15 (4) ◽  
pp. 478-486
Author(s):  
Sheng-Biao An ◽  
Li-Xin Zhao ◽  
Shi-Cong Yang ◽  
Tao An ◽  
Rui-Xia Yang
Keyword(s):  
Power Consumption ◽  
Successive Approximation ◽  
Dynamic Range ◽  
Sar Adc ◽  
Total Power ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Successive Approximation Register ◽  
Total Power Consumption

This paper presents a charge redistributed successive approximation register analog-to-digital converter (SAR ADC). Compared with the traditional Digital-Analog Convertor (DAC), the power consumption of the DAC scheme is reduced by 90%, the area is reduced by 60%. The test chip fabricated in 180 nm Complementary Metal Oxide Semiconductor (CMOS) occupied an active area of 0.12 mm 2 . At 10 MS/s, a signal-to-noise and distortion ratio (SNDR) of 57.70 dB and a spurious-free dynamic range (SFDR) of 55.63 dB are measured with 1.68 Vpp differential-mode input signal. The total power consumption is 690 μW corresponding to 67 fJ/conversion step figure of merit.

Design of a 10-Bit High Performance Current-Steering DAC with a Novel Nested Decoder Based on Domino Logic

2015 ◽  
Vol 24 (06) ◽  
pp. 1550086 ◽  
Author(s):  
Masoud Nazari ◽  
Leila Sharifi ◽  
Meysam Akbari ◽  
Omid Hashemipour
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Dynamic Range ◽  
Logic Gates ◽  
Cmos Technology ◽  
Total Power ◽  
Current Steering ◽  
Domino Logic ◽  
Chip Area ◽  
Total Power Consumption

In this paper, a 10-bit 8-2 segmented current-steering digital-to-analog converter (DAC) is presented which uses a novel nested binary to thermometer (BT) decoder based on domino logic gates. High accuracy and high performances are achieved with this structure. The proposed decoder has a pipelining scheme and it is designed symmetrically in three stages with repeatable logic gates. Thus, power consumption, chip area and the number of control signals are reduced. The proposed DAC is simulated in 0.18-μm CMOS technology and the spurious-free dynamic range (SFDR) is 65.3 dB over a 500 MHz output bandwidth at 1 GS/s. Total power consumption of the designed DAC is only 23.4 mW while the digital and analog supply voltages are 1.2 and 1.8 V, respectively. The active area of the proposed DAC is equal to 0.3 mm2.

A 12-bit 1-MS/s 26-μW SAR ADC for Sensor Applications

2018 ◽  
Vol 3 (1) ◽  
Author(s):  
Yung-Hui Chung ◽  
Chia-Wei Yen ◽  
Cheng-Hsun Tsai
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Total Power ◽  
Measured Signal ◽  
Input Frequency ◽  
Dynamic Comparator ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Sensor Applications ◽  
Total Power Consumption

AbstractThis chapter presents an energy-efficient 12-bit 1-MS/s successive approximation register analog-to-digital converter (ADC) for sensor applications. A programmable dynamic comparator is proposed to suppress static current and maintain good linearity. A hybrid charge redistribution digital-to-analog converter is proposed to decrease the total capacitance, which would reduce the power consumption of the input and reference buffers. In the proposed ADC, its total input capacitance is only 700 fF, which greatly reduces the total power consumption of the analog frontend circuits. The 12-bit ADC is fabricated using 0.18-μm complementary metal-oxidesemiconductor technology, and it consumes only 26 μW from a 1 V supply at 1-MS/s. The measured signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 60.1 and 72.6 dB, respectively. The measured effective number of bits (ENOB) for a 100 kHz input frequency is 9.7 bits. At the Nyquist input frequency, the measured SNDR and SFDR are 59.7 and 71 dB, respectively. The ENOB is maintained at 9.6 bits and the figure-of-merit is 33.5 fJ/conversion-step.

A 12-Bit 500-MS/s Current Steering CMOS DAC for High-Speed PLC Modems

2016 ◽  
Vol 25 (10) ◽  
pp. 1650122 ◽  
Author(s):  
Chan-Keun Kwon ◽  
Junil Moon ◽  
Soo-Won Kim
Keyword(s):  
High Speed ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Design Procedure ◽  
Weighted Averaging ◽  
Total Power ◽  
Cmos Process ◽  
Current Steering ◽  
Current Cell ◽  
Total Power Consumption

A 12-bit 500-MS/s current steering digital-to-analog converter (DAC) for high-speed power line communication (PLC) modems is presented in this paper. The performance of current steering DAC is limited by the current cell mismatches and glitch problems caused by switching timing errors. In this paper, the current cell design procedure is presented to minimize random mismatches. Then, a new data-weighted averaging (DWA) technique with fewer glitches and low hardware complexity is proposed to compensate for the gradient mismatch. Spurious-free dynamic range (SFDR) improvement and low complexity are effectively achieved by employing both a row–column structure and a (CSA) structure as the floor plan of the proposed DAC. The proposed DAC is implemented in a standard 0.18-[Formula: see text]m CMOS process with an active area of 2.445[Formula: see text]mm2, which achieves a differential non linearity (DNL) of 0.25[Formula: see text]LSB and an integral non-linearity (INL) of 0.19[Formula: see text]LSB. Additionally, the SFDR increases by 13.2[Formula: see text]dB (on average) when employing the proposed DWA technique. The total power consumption of the proposed DAC is 176[Formula: see text]mW from a 1.8-V supply voltage.

scholarly journals A 28 nm CMOS 100 MHz 67 dB-Dynamic-Range 968 µW Flipped-Source-Follower Analog Filter

2021 ◽  
Vol 11 (2) ◽  
pp. 15
Author(s):  
Marcello De Matteis ◽  
Federico Fary ◽  
Elia A. Vallicelli ◽  
Andrea Baschirotto
Keyword(s):  
Dynamic Range ◽  
Power Reduction ◽  
Total Power ◽  
Noise Power ◽  
Analog Filter ◽  
Figures Of Merit ◽  
Total Power Consumption ◽  
Source Follower ◽  
Order Continuous ◽  
28 Nm

This paper presents a fourth-order continuous-time analog filter based on the cascade of two flipped-source-follower (FSF) biquadratic (biquad) cells. The FSF biquad adopts two interacting loops (the first due to the classic source-follower, and the second to the additional gain path) which lower the impedances of all circuit nodes with relevant benefits in terms of noise power reduction and linearity enhancement. The presented device was integrated in 28 nm CMOS and featured 100 MHz −3 dB bandwidth with 67 dB Dynamic-Range. Input IP3 was 12 dBm at 10 and 11 MHz input tone frequencies. Total power consumption was 0.968 mW (0.484 mW per cell). Hence, the filter performed one of the highest figures-of-merit (160.7 dBJ-1) compared with analog state-of-the-art filters.

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