Enhancement in Retention Time of 3TDRAM Using Double Gate Finfet Technology at Nanometer Regime.

2021 ◽  
pp. 359-370
Author(s):  
Amol S. Sankpala, D. J. Peteb
Keyword(s):  
Leakage Current ◽  
Retention Time ◽  
Integrated Circuit ◽  
Supply Voltage ◽  
Average Power ◽  
Random Access ◽  
Cmos Technology ◽  
Double Gate ◽  
Silicon Area ◽  
Nanometer Regime

Leakage current, power and area is the key challenges for VLSI designer during implementation of low power devices. In an integrated circuit number of transistors double in small silicon area every two years. There are certain limitations of cmos technology in nanometer regime out of which leakage current, leakage power, average current and average power is an important issues. In this paper, Retention time improvement in three transistor dynamic random access memory using double gate Finfet technology is proposed. Double gate finfet technology in 3TDRAM overcomes the issues related to cmos technology and it does not required additional circuitry. Proposed 3T DRAM is investigated with cmos and finfet technology at 90nm technology using cadence tool. Analysis of 3TDRAM using cmos and double gate finfet technology is carried out by variation in supply voltage and capacitance values. In double gate finfet technology leakage parameters are minimized and retention time(Th) is more improved as compared to cmos technology is observed.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

scholarly journals Design of area-efficient GHz range current mode frequency synthesizer using standard CMOS technology

2019 ◽  
Vol 70 (4) ◽  
pp. 323-328
Author(s):  
Dan-Dan Zheng ◽  
Yu-Bin Li ◽  
Chang-Qi Wang ◽  
Kai Huang ◽  
Xiao-Peng Yu
Keyword(s):  
Frequency Synthesizer ◽  
Frequency Tuning ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Mode Frequency ◽  
Loop Filter ◽  
Silicon Area ◽  
Power Efficient ◽  
A Current

Abstract In this paper, an area and power efficient current mode frequency synthesizer for system-on-chip (SoC) is proposed. A current-mode transformer loop filter suitable for low supply voltage is implemented to remove the need of a large capacitor in the loop filter, and a current controlled oscillator with additional voltage based frequency tuning mechanism is designed with an active inductor. The proposed design is further integrated with a fully programmable frequency divider to maintain a good balance among output frequency operating range, power consumption as well as silicon area. A test chip is implemented in a standard 0.13 µm CMOS technology, measurement result demonstrates that the proposed design has a working range from 916 MHz to 1.1 l GHz and occupies a silicon area of 0.25 mm2 while consuming 8.4 mW from a 1.2 V supply.

A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA

2013 ◽  
Vol 22 (10) ◽  
pp. 1340033 ◽  
Author(s):  
HONGLIANG ZHAO ◽  
YIQIANG ZHAO ◽  
YIWEI SONG ◽  
JUN LIAO ◽  
JUNFENG GENG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Readout Integrated Circuit ◽  
Chip Area ◽  
Operating Modes

A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm2. By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm2.

scholarly journals A CMOS Programmable Fourth-Order Butterworth Active-RC Low-Pass Filter

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 204 ◽  
Author(s):  
Changchun Zhang ◽  
Long Shang ◽  
Yongkai Wang ◽  
Lu Tang
Keyword(s):  
Radio Frequency Identification ◽  
Supply Voltage ◽  
Cutoff Frequency ◽  
Cmos Technology ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Silicon Area ◽  
Fully Differential ◽  
Low Pass ◽  
Low Sensitivity

This paper presents a low-pass filter (LPF) for an ultra-high frequency (UHF) radio frequency identification (RFID) reader transmitter in standard SMIC 0.18 μm CMOS technology. The active-RC topology and Butterworth approximation function are employed mainly for high linearity and high flatness respectively. Two cascaded fully-differential Tow-Thomas biquads are chosen for low sensitivity to process errors and strong resistance to the imperfection of the involved two-stage fully-differential operational amplifiers. Besides, the LPF is programmable in order to adapt to the multiple data rate standards. Measurement results show that the LPF has the programmable bandwidths of 605/870/1020/1330/1530/2150 kHz, the optimum input 1dB compression point of −7.81 dBm, and the attenuation of 50 dB at 10 times cutoff frequency, with the overall power consumption of 12.6 mW from a single supply voltage of 1.8 V. The silicon area of the LPF core is 0.17 mm2.

scholarly journals Low-Power High-Speed Double Gate 1-bit Full Adder Cell

2016 ◽  
Vol 62 (4) ◽  
pp. 329-334 ◽  
Author(s):  
Raushan Kumar ◽  
Sahadev Roy ◽  
C.T. Bhunia
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Average Power ◽  
Full Adder ◽  
Cmos Technology ◽  
Spice Simulation ◽  
Pass Transistor ◽  
Voltage Swing

Abstract In this paper, we proposed an efficient full adder circuit using 16 transistors. The proposed high-speed adder circuit is able to operate at very low voltage and maintain the proper output voltage swing and also balance the power consumption and speed. Proposed design is based on CMOS mixed threshold voltage logic (MTVL) and implemented in 180nm CMOS technology. In the proposed technique the most time-consuming and power consuming XOR gates and multiplexer are designed using MTVL scheme. The maximum average power consumed by the proposed circuit is 6.94μW at 1.8V supply voltage and frequency of 500 MHz, which is less than other conventional methods. Power, delay, and area are optimized by using pass transistor logic and verified using the SPICE simulation tool at desired broad frequency range. It is also observed that the proposed design may be successfully utilized in many cases, especially whenever the lowest power consumption and delay are aimed.

Multiferroic Memory: A Disruptive Technology or Future Technology?

2012 ◽  
Vol 189 ◽  
pp. 1-14 ◽  
Author(s):  
Ashok Kumar ◽  
Nora Ortega ◽  
Sandra Dussan ◽  
Shalini Kumari ◽  
Dilsom Sanchez ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Magnetic Fields ◽  
Electric Fields ◽  
Integrated Circuit ◽  
Room Temperature ◽  
Bismuth Ferrite ◽  
Random Access ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Disruptive Technology

The term "Multiferroic" is coined for a material possessing at least two ferroic orders in the same or composite phase (ferromagnetic, ferroelectric, ferroelastic); if the first two ferroic orders are linearly coupled together it is known as a magnetoelectric (ME) multiferroic. Two kinds of ME multiferroic memory devices are under extensive research based on the philosophy of "switching of polarization by magnetic fields and magnetization by electric fields." Successful switching of ferroic orders will provide an extra degree of freedom to create more logic states. The "switching of polarization by magnetic fields" is useful for magnetic field sensors and for memory elements if, for example, polarization switching is via a very small magnetic field from a coil underneath an integrated circuit. The electric control of magnetization is suitable for nondestructive low-power, high-density magnetically read and electrically written memory elements. If the system possesses additional features, such as propagating magnon (spin wave) excitations at room temperature, additional functional applications may be possible. Magnon-based logic (magnonic) systems have been initiated by various scientists, and prototype devices show potential for future complementary metal oxide semiconductor (CMOS) technology. Discovery of high polarization, magnetization, piezoelectric, spin waves (magnon), magneto-electric, photovoltaic, exchange bias coupling, etc. make bismuth ferrite, BiFeO3, one of the widely investigated materials in this decade. Basic multiferroic features of well known room temperature single phase BiFeO3in bulk and thin films have been discussed. Functional magnetoelectric (ME) properties of some lead-based solid solution perovskite multiferroics are presented and these systems also have a bright future. The prospects and the limitations of the ME-based random access memory (MERAM) are explained in the context of recent discoveries and state of the art research.

Time-Domain Readout of 1T–1C DRAM Cells

2017 ◽  
Vol 27 (01) ◽  
pp. 1850005 ◽  
Author(s):  
Sherif M. Sharroush
Keyword(s):  
Time Domain ◽  
Noise Analysis ◽  
Average Power ◽  
Random Access ◽  
Voltage Divider ◽  
Cmos Technology ◽  
Access Time ◽  
Technology Scaling ◽  
Sense Amplifier ◽  
Power Delay Product

The conventional readout of one-transistor–one-capacitor dynamic random-access memories (1T–1C DRAMs) depends on using a sense amplifier to develop the bitline voltage and settle it to the voltage of the power supply, [Formula: see text], or to 0[Formula: see text]V depending on whether the stored data is “1” or “0,” respectively. However, using the sense amplifier makes the reading process sluggish. In this paper, a capacitive-voltage divider-based readout scheme is proposed. According to this scheme, the developed bitline voltage is converted into a pulse with a certain starting time. Specifically, this pulse appears at a later time in case of “0” storage than that if a “1” is stored, thus the proposed scheme is aptly called “time-domain readout.” The effects of parameter and component mismatches and technology scaling on the proposed scheme are investigated. The proposed scheme is analyzed quantitatively with a suggestion given to widen the time gap between the starting times of the pulses corresponding to the “0” and “1” states. The proposed scheme is verified by simulation adopting the 45 nm CMOS technology with [Formula: see text][Formula: see text]V. According to the simulation results, percentage savings of 68.8%, 56.8%, and 32% in the read-access time, the read-cycle time, and the average power-delay product, respectively, are shown. The proposed scheme requires approximately 40% extra area overhead for the reading circuitry. Also, a noise analysis is performed and it is found that the device noise does not affect the proposed scheme significantly.

scholarly journals Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction Techniques

2018 ◽  
Vol 8 (6) ◽  
pp. 4922
Author(s):  
Anil Khatak ◽  
Manoj Kumar ◽  
Sanjeev Dhull
Keyword(s):  
Power Consumption ◽  
Leakage Current ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Power Reduction ◽  
Total Power ◽  
Low Power Consumption ◽  
Power Gating ◽  
Reduction Techniques ◽  
Total Power Consumption

To reduce power consumption of regenerative comparator three different techniques are incorporated in this work. These techniques provide a way to achieve low power consumption through their mechanism that alters the operation of the circuit. These techniques are pseudo NMOS, CVSL (cascode voltage switch logic)/DCVS (differential cascode voltage switch) & power gating. Initially regenerative comparator is simulated at 90 nm CMOS technology with 0.7 V supply voltage. Results shows total power consumption of 15.02 μW with considerably large leakage current of 52.03 nA. Further, with pseudo NMOS technique total power consumption increases to 126.53 μW while CVSL shows total power consumption of 18.94 μW with leakage current of 1270.13 nA. More then 90% reduction is attained in total power consumption and leakage current by employing the power gating technique. Moreover, the variations in the power consumption with temperature is also recorded for all three reported techniques where power gating again show optimum variations with least power consumption. Four more conventional comparator circuits are also simulated in 90nm CMOS technology for comparison. Comparison shows better results for regenerative comparator with power gating technique. Simulations are executed by employing SPICE based on 90 nm CMOS technology.

scholarly journals Advantageous Sampling of Correlated Current Signals to Supress Fixed-Pattern Noise in CMOS Imagers

2017 ◽  
Vol 12 (1) ◽  
pp. 47-55
Author(s):  
R. A. Souza ◽  
L. G. M. Ventura ◽  
A. R. S. Martins ◽  
D. W. de Lima Monteiro ◽  
L. P. Salles
Keyword(s):  
Integrated Circuit ◽  
Supply Voltage ◽  
Process Variations ◽  
Current Mode ◽  
Physical Parameters ◽  
Basic Operation ◽  
Silicon Area ◽  
Cmos Imagers ◽  
Pattern Noise ◽  
Fixed Pattern Noise

The Active Pixel Sensor (APS) has been a vastly used integrated circuit topology in CMOS imagers. Mismatch of physical parameters among pixels, caused by process variations, introduces Fixed-Pattern Noise (FPN) at the array output. Correlated Double Sampling (CDS) in voltage mode is a commonly used method to suppress the offset caused FPN. However, it increases the complexity as well as the demanded silicon area of either the pixel or the external circuitry, besides having its signal swing restricted by the supply voltage. An alternative CDS circuit operating in current mode to reduce FPN is presented in this paper. The correlated current signals are sampled and subtracted using a simpler circuitry, leading to a more efficient relation of FPN reduction for the required silicon area. Furthermore, this technique does not change the APS topology or basic operation cycle. A simulated and tested CDS alternative is presented, and a simulated further improved version is proposed. Simulation and experiments showed a 40% FPN reduction with the fabricated CDS, whereas the improved simulated version ensures 90% FPN reduction.

A ROBUST HIGH-SPEED LOW INPUT IMPEDANCE CMOS CURRENT COMPARATOR

2008 ◽  
Vol 17 (06) ◽  
pp. 1139-1149 ◽  
Author(s):  
VARAKORN KASEMSUWAN ◽  
SURACHET KHUCHAROENSIN
Keyword(s):  
Input Impedance ◽  
High Speed ◽  
Supply Voltage ◽  
Average Power ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Circuit Performance ◽  
Current Comparator ◽  
Low Input ◽  
Voltage Conversion

In this paper, a robust high-speed low input impedance CMOS current comparator is proposed. The front end of the comparator uses the modified Wilson current-mirror and diode-connected transistors to perform a current subtraction and current to voltage conversion simultaneously. The circuit is immune to the process variation and has low input impedances. HSPICE is used to verify the circuit performance with a 0.5 μm CMOS technology. The simulation results show the propagation delay of 1.67 ns, input impedances of 123 Ω, and 126 Ω, and average power dissipation of 0.63 mW for ± 0.1 μA input current under the supply voltage of 3 V.

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