scholarly journals Dual-edge triggered pulsed flip-flop with high performance and high soft-error tolerance

2011 ◽  
Author(s):  
Jianping Gong
Keyword(s):  
High Performance ◽  
Soft Error ◽  
Error Tolerance ◽  
Flip Flop

scholarly journals Categorization and SEU Fault Simulations of Radiation-Hardened-by-Design Flip-Flops

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1572
Author(s):  
Ehab A. Hamed ◽  
Inhee Lee
Keyword(s):  
Soft Error ◽  
Error Tolerance ◽  
Cmos Process ◽  
Flip Flop ◽  
Single Event Upsets ◽  
Area Overhead ◽  
Fair Comparison ◽  
Reference Design ◽  
Radiation Hardened ◽  
Radiation Hardened By Design

In the previous three decades, many Radiation-Hardened-by-Design (RHBD) Flip-Flops (FFs) have been designed and improved to be immune to Single Event Upsets (SEUs). Their specifications are enhanced regarding soft error tolerance, area overhead, power consumption, and delay. In this review, previously presented RHBD FFs are classified into three categories with an overview of each category. Six well-known RHBD FFs architectures are simulated using a 180 nm CMOS process to show a fair comparison between them while the conventional Transmission Gate Flip-Flop (TGFF) is used as a reference design for this comparison. The results of the comparison are analyzed to give some important highlights about each design.

Design and Comparison of High-Reliable Radiation-Hardened Flip-Flops Under SMIC 40nm Process

2016 ◽  
Vol 25 (12) ◽  
pp. 1650163 ◽  
Author(s):  
Bingbing Xia ◽  
Jun Wu ◽  
Hongjin Liu ◽  
Kai Zhou ◽  
Zhifu Miao
Keyword(s):  
High Performance ◽  
High Reliability ◽  
Soft Error ◽  
Advanced Technology ◽  
Flip Flop ◽  
Aerospace Applications ◽  
Technology Process ◽  
Radiation Hardened ◽  
Power Radiation ◽  
Error Robustness

With the need for fast and low-power radiation-hardened processors, advanced technology process is applied to obtain both high performance as well as high reliability. However, scaling down of the size of the transistor makes the transistor sensitive to outside disturbances, such as soft error introduced by the strikes of the cosmic neutron beams. Besides aerospace applications, such reliability should also be taken into consideration for the sub-100[Formula: see text]nm CMOS designs to ensure the robustness of the circuit. In such circumstances, several radiation-hardened flip-flops are designed and simulated under SMIC 40[Formula: see text]nm process. Simulation results show that with five aspects (performance, power, area, PVT variation and reliability) taken into consideration, TSPC-based DICE and TMR combined architecture has the best soft-error robustness in comparison with other radiation-hardened flip-flops, and the critical charge of such architecture is 490[Formula: see text]fC, which is 12.5X higher than the traditional unhardened flip-flop.

scholarly journals Soft Error Susceptibility Analysis of SRAM-Based FPGAs in High-Performance Information Systems

2007 ◽  
Vol 54 (6) ◽  
pp. 2714-2726 ◽  
Author(s):  
Hossein Asadi ◽  
Mehdi B. Tahoori ◽  
Brian Mullins ◽  
David Kaeli ◽  
Kevin Granlund
Keyword(s):  
Information Systems ◽  
High Performance ◽  
Soft Error ◽  
Performance Information ◽  
Susceptibility Analysis

scholarly journals Low Power based Dynamic TSPC D flip flop for High Performance Applications

2020 ◽  
Vol 9 (8) ◽  
pp. 758-762
Keyword(s):  
Low Power ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
Memory Cell ◽  
Research Center ◽  
Short Channel ◽  
Flip Flop ◽  
Force Application ◽  
Effect Transistor

D flip-flop is viewed as the most basic memory cell in by far most of computerized circuits, which brings it broad usage, particularly under current conditions where high-thickness pipeline innovation is as often as possible utilized in advanced coordinated circuits and flip-flop modules are key segments. As a constant research center, various sorts of zero flip-flops have been concocted and explored, and the ongoing exploration pattern has gone to rapid low-control execution, which can be come down to low power-defer item. To actualize superior VLSI, picking the most proper D flip-flop has clearly become an incredibly huge part in the structure stream. The quick headway in semiconductor innovation made it practicable to coordinate entire electronic framework on a solitary chip. CMOS innovation is the most doable semiconductor innovation yet it neglects to proceed according to desires past and at 32nm innovation hub because of the short channel impacts. GNRFET is Graphene Nano Ribbon Field Effect Transistor, it is seen that GNRFET is a promising substitute for low force application for its better grasp over the channel. In this paper, an audit on Dynamic Flip Flop and GNRFET is introduced. The power is improved in the proposed circuit for the D flip flop TSPC.

scholarly journals A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER

2013 ◽  
pp. 78-82
Author(s):  
GOPALA KRISHNA.M ◽  
UMA SANKAR.CH ◽  
NEELIMA. S ◽  
KOTESWARA RAO.P
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Flip Flop ◽  
Ring Counter ◽  
Double Edge ◽  
Low Power Cmos ◽  
Cmos Vlsi

In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.

scholarly journals FAILURE TOLERANT SYNCHRONOUS AND SELT-TIED CIRCUITS COMPARISON

2021 ◽  
Author(s):  
Aleksandr Zatsarinny ◽  
Yuri Stepchenkov ◽  
Yuri Diachenko ◽  
Yuri Rogdestvenski
Keyword(s):  
Digital Circuits ◽  
Soft Error ◽  
Error Tolerance ◽  
Electronic Circuits ◽  
Two Phase ◽  
Synchronous Circuits ◽  
Tolerance Level ◽  
Failure Tolerance ◽  
Hardware Costs ◽  
Signal Coding

The article considers the problem of developing synchronous and self-timed (ST) digital circuits that are tolerant to soft errors. Synchronous circuits traditionally use the 2-of-3 voting principle to ensure single failure, resulting in three times the hardware costs. In ST circuits, due to dual-rail signal coding and two-phase control, even duplication provides a soft error tolerance level 2.1 to 3.5 times higher than the triple modular redundant synchronous counterpart. The development of new high-precision software simulating microelectronic failure mechanisms will provide more accurate estimates for the electronic circuits' failure tolerance

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