A low power CMOS design of an all digital phase locked loop

Mapping Intimacies ◽

10.17760/d20001051 ◽

2011 ◽

Author(s):

Jun Zhao

Keyword(s):

Low Power ◽

Phase Locked Loop ◽

Digital Phase ◽

Cmos Design ◽

Low Power Cmos

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Low-power CMOS design through VTH control and low-swing circuits

Proceedings of 1997 International Symposium on Low Power Electronics and Design ◽

10.1145/263272.263273 ◽

1997 ◽

Cited By ~ 14

Author(s):

Takayasu Sakurai ◽

Hiroshi Kawaguchi ◽

Tadahiro Kuroda

Keyword(s):

Low Power ◽

Cmos Design ◽

Low Power Cmos

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Design of a Low Power Schottky TTL High-Speed Digital Phase-Locked Loop Integrated Circuit.

10.21236/ada094729 ◽

1980 ◽

Author(s):

James D. Gallia

Keyword(s):

Low Power ◽

Integrated Circuit ◽

High Speed ◽

Phase Locked Loop ◽

Digital Phase

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Low Power CMOS Design for Radio Frequencies

Ultra-Low Power Wireless Technologies for Sensor Networks ◽

10.1007/978-0-387-49313-8_2 ◽

2007 ◽

pp. 13-39

Keyword(s):

Low Power ◽

Cmos Design ◽

Low Power Cmos ◽

Radio Frequencies

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Low voltage low power CMOS design techniques for deep submicron ICs

VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design ◽

10.1109/icvd.2000.812579 ◽

2002 ◽

Cited By ~ 20

Author(s):

Liqiong Wei ◽

K. Roy ◽

V.K. De

Keyword(s):

Low Power ◽

Low Voltage ◽

Deep Submicron ◽

Cmos Design ◽

Low Power Cmos ◽

Design Techniques

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Design and Analysis of a Low Power Digital Phase Locked Loop

2016 8th International Conference on Computational Intelligence and Communication Networks (CICN) ◽

10.1109/cicn.2016.60 ◽

2016 ◽

Cited By ~ 2

Author(s):

Deepak Bhati ◽

Balwinder Singh

Keyword(s):

Low Power ◽

Phase Locked Loop ◽

Digital Phase

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A 2.4-GHz low-power all-digital phase-locked loop

2009 IEEE Custom Integrated Circuits Conference ◽

10.1109/cicc.2009.5280832 ◽

2009 ◽

Cited By ~ 8

Author(s):

Liangge Xu ◽

Saska Lindfors ◽

Kari Stadius ◽

Jussi Ryynanen

Keyword(s):

Low Power ◽

Phase Locked Loop ◽

Digital Phase

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Low power CMOS design strategies

32nd Design Automation Conference ◽

10.1145/196244.196574 ◽

1994 ◽

Cited By ~ 1

Author(s):

Matthias Schoebinger ◽

Tobias G. Noll

Keyword(s):

Low Power ◽

Design Strategies ◽

Cmos Design ◽

Low Power Cmos

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Low-power digital phase locked loop utilizes CMOS logic

Microelectronics Reliability ◽

10.1016/0026-2714(72)90437-4 ◽

1972 ◽

Vol 11 (5) ◽

pp. 418

Keyword(s):

Low Power ◽

Phase Locked Loop ◽

Digital Phase

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A 1.7mW All Digital Phase-Locked Loop with New Gain Generator and Low Power DCO

2006 IEEE International Conference on Acoustics Speed and Signal Processing Proceedings ◽

10.1109/iscas.2006.1693721 ◽

2006 ◽

Author(s):

Tzu-Chiang Chao ◽

Wei Hwang

Keyword(s):

Low Power ◽

Phase Locked Loop ◽

Digital Phase

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Evaluation of charge recovery circuits and adiabatic switching for low power CMOS design

Proceedings of 1994 IEEE Symposium on Low Power Electronics ◽

10.1109/lpe.1994.573221 ◽

2002 ◽

Cited By ~ 9

Author(s):

T. Indermaur ◽

M. Horowitz

Keyword(s):

Low Power ◽

Cmos Design ◽

Adiabatic Switching ◽

Low Power Cmos ◽

Charge Recovery

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