Design and Analysis of a Low Power Digital Phase Locked Loop

2016 ◽  
Author(s):  
Deepak Bhati ◽  
Balwinder Singh
Keyword(s):  
Low Power ◽  
Phase Locked Loop ◽  
Digital Phase

A 2.4-GHz low-power all-digital phase-locked loop

2009 ◽  
Author(s):  
Liangge Xu ◽  
Saska Lindfors ◽  
Kari Stadius ◽  
Jussi Ryynanen
Keyword(s):  
Low Power ◽  
Phase Locked Loop ◽  
Digital Phase

scholarly journals Design and Simulation of Low Power Consuming Digital Controlled Oscillator in All Digital Phase Locked Loop

2019 ◽  
Vol 8 (12) ◽  
pp. 3801-3806
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Phase Locked Loop ◽  
Biomedical Implant ◽  
Digital Phase ◽  
Rf Transceivers ◽  
Technology Innovations ◽  
History Of ◽  
Previous Design ◽  
Delay Elements

Recent IC technology innovations can achieve lowpowe r biomedical implant functionality.RF transceivers require low-power and small-sized components in biomedical implants to achieve the best results in frequency and phase control. Phase Locked Loop (PLL) is the key component for controlling these parameters in low power consumption RF transceivers. Therefore All Digital Phase Locked Loop (ADPLL) is chipping effectively into a major role in the fields of Biomedical & Communication. ADPLLs contribute better results in these areas due to their efficient blocks. This paper focuses on the design of low-power Digital Controlled Oscillator (DCO) and provides information on the various ADPLL blocks. To reduce power dissipation DCO is designed with XNOR gate using delay elements by avoiding direct contact between VDD & GND and the MOS transistors were arranged in ring topology. Tanner tools were used to design and simulation. In addition to this it also provides the detailed history of PLLs & ADPLLs and their mathematical analysis. Compared to previous design, the current DCO design gives better power consumption results.

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