scholarly journals Quantum-dot cellular automata based reversible low power parity generator and parity checker design for nanocommunication

2016 ◽  
Vol 17 (3) ◽  
pp. 224-236 ◽  
Author(s):  
Jadav Chandra Das ◽  
Debashis De
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Low Power ◽  
Power Parity ◽  
Quantum Dot Cellular Automata ◽  
Parity Checker ◽  
Parity Generator

Design & Analysis of Novel Non-Reversible & Reversible Parity Generator & Detector in Quantum Cellular Automata using Feynman Gate

2021 ◽  
Vol 13 ◽  
Author(s):  
Neeraj Tripathi ◽  
Mohammad Mudakir Fazili ◽  
Rahil Jahangir
Keyword(s):  
Energy Dissipation ◽  
Cellular Automata ◽  
Quantum Dot ◽  
Low Power ◽  
Fault Tolerant ◽  
Design Parameters ◽  
Logic Function ◽  
Ultra Low Power ◽  
Quantum Dot Cellular Automata ◽  
Parity Generator

Aim: A novel design for non-reversible as well as reversible parity generator and detector in Quantum-dot Cellular Automata (QCA) technology is presented in this research article. Parity generator and detector circuits are reliable error-checking components of a nano-communication system. Objective: The main focus of this research is to design an ultra-low-power fault-tolerant reversible gate implementation of the parity logic function in QCA. An efficient QCA design layout with minimal area, less latency and the least energy dissipation is desired. Methods: The proposed designs are developed using Quantum-dot Cellular Automata (QCA) technology. The circuits are optimized using majority gate reduction and clock zone reduction techniques. Also, the cell-cell interaction technique is employed to further optimize the QCA circuit. To increase the fault tolerance and for ultra-low power operation, reversible QCA circuits are designed using cascaded Feynman gates. Results and Conclusion: The efficiency of the parity generator and detector is calculated to be more than 25% compared to existing QCA layouts. It is demonstrated in this paper that the proposed circuits perform exceptionally well on every design parameter. The design parameters under consideration are cell count, cell area, complexity, crossover count, latency and energy dissipation. Using reversible logic, a fault-tolerant and defect-sensitive circuit is developed for parity generation and detection.

scholarly journals Gray‐code adder with parity generator – a novel quantum‐dot cellular automata implementation

2020 ◽  
Vol 14 (2) ◽  
pp. 243-250 ◽  
Author(s):  
Luiz G.L. Vieira ◽  
Luiz F.M. Vieira ◽  
Marcos A.M. Vieira ◽  
Omar P. Vilela Neto
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Gray Code ◽  
Quantum Dot Cellular Automata ◽  
Parity Generator

scholarly journals Low power design methodology in quantum-dot cellular automata

2022 ◽  
Vol 97 ◽  
pp. 107638
Author(s):  
Arindam Sadhu ◽  
Kunal Das ◽  
Debashis De ◽  
Maitreyi Ray Kanjilal
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Low Power ◽  
Design Methodology ◽  
Low Power Design ◽  
Quantum Dot Cellular Automata

scholarly journals An Efficient Design of DCT Approximation Based on Quantum Dot Cellular Automata (QCA) Technology

2019 ◽  
Vol 2019 ◽  
pp. 1-11 ◽  
Author(s):  
Ismail Gassoumi ◽  
Lamjed Touil ◽  
Bouraoui Ouni ◽  
Abdellatif Mtibaa
Keyword(s):  
Image Processing ◽  
Cellular Automata ◽  
Quantum Dot ◽  
Low Power ◽  
Video Compression ◽  
Video Processing ◽  
Power Dissipation ◽  
Functional Verification ◽  
Efficient Design ◽  
Quantum Dot Cellular Automata

Optimization for power is one of the most important design objectives in modern digital image processing applications. The DCT is considered to be one of the most essential techniques in image and video compression systems, and consequently a number of extensive works had been carried out by researchers on the power optimization. On the other hand, quantum-dot cellular automata (QCA) can present a novel opportunity for the design of highly parallel architectures and algorithms for improving the performance of image and video processing systems. Furthermore, it has considerable advantages in comparison with CMOS technology, such as extremely low power dissipation, high operating frequency, and a small size. Therefore, in this study, the authors propose a multiplier-less DCT architecture in QCA technology. The proposed design provides high circuit performance, very low power consumption, and very low dimension outperform to the existing conventional structures. The QCADesigner tool has been utilized for QCA circuit design and functional verification of all designs in this work. QCAPro, a very widespread power estimator tool, is applied to estimate the power dissipation of the proposed circuit. The suggested design has 53% improvement in terms of power over the conventional solution. The outcome of this work can clearly open up a new window of opportunity for low power image processing systems.

scholarly journals Editorial for the Special Issue on “Quantum-Dot Cellular Automata (QCA) and Low Power Application”

2018 ◽  
Vol 8 (4) ◽  
pp. 40
Author(s):  
Stefania Perri
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Consumption ◽  
Low Power ◽  
Special Issue ◽  
Innovative Technologies ◽  
Quantum Dot Cellular Automata ◽  
Power Application

Challenges created by the trend of increasingly reducing the size of transistors have made necessary innovative technologies to limit undesirable impacts on the performance speed and power consumption of future designs. [...]

Sign in / Sign up

Export Citation Format

Share Document