Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs

Koichi FUJIWARA; Kazushi KAWAMURA; Masao YANAGISAWA; Nozomu TOGAWA

doi:10.1587/transfun.e99.a.1294

Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e99.a.1294 ◽

2016 ◽

Vol E99.A (7) ◽

pp. 1294-1310 ◽

Cited By ~ 2

Author(s):

Koichi FUJIWARA ◽

Kazushi KAWAMURA ◽

Masao YANAGISAWA ◽

Nozomu TOGAWA

Keyword(s):

High Level Synthesis ◽

Clock Skew ◽

High Level

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Clock skew estimate modeling for FPGA high-level synthesis and its application

2015 IEEE 11th International Conference on ASIC (ASICON) ◽

10.1109/asicon.2015.7516905 ◽

2015 ◽

Cited By ~ 1

Author(s):

Koichi Fujiwara ◽

Kazushi Kawamura ◽

Masao Yanagisawa ◽

Nozomu Togawa

Keyword(s):

High Level Synthesis ◽

Clock Skew ◽

High Level

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Register binding and domain assignment for multi-domain clock skew scheduling-aware high-level synthesis

Thirteenth International Symposium on Quality Electronic Design (ISQED) ◽

10.1109/isqed.2012.6187579 ◽

2012 ◽

Author(s):

Keisuke Inoue ◽

Mineo Kaneko

Keyword(s):

High Level Synthesis ◽

Clock Skew ◽

Domain Assignment ◽

Clock Skew Scheduling ◽

High Level

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A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration

2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ◽

10.1109/vlsi-dat.2016.7482547 ◽

2016 ◽

Cited By ~ 2

Author(s):

Koichi Fujiwara ◽

Kazushi Kawamura ◽

Masao Yanagisawa ◽

Nozomu Togawa

Keyword(s):

Critical Path ◽

High Level Synthesis ◽

Clock Skew ◽

Synthesis Algorithm ◽

High Level

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Power-Aware High-Level Synthesis With Clock Skew Management

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2010.2091292 ◽

2012 ◽

Vol 20 (1) ◽

pp. 167-171 ◽

Cited By ~ 1

Author(s):

Tung-Hua Yeh ◽

Sying-Jyan Wang

Keyword(s):

High Level Synthesis ◽

Clock Skew ◽

High Level

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Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits

17th Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.2012.6164953 ◽

2012 ◽

Author(s):

Wen-Pin Tu ◽

Shih-Hsu Huang ◽

Chun-Hua Cheng

Keyword(s):

High Level Synthesis ◽

Clock Skew ◽

Clock Period ◽

Minimum Area ◽

Area Overhead ◽

High Level

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Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e92.a.3169 ◽

2009 ◽

Vol E92-A (12) ◽

pp. 3169-3179 ◽

Cited By ~ 7

Author(s):

Akira OHCHI ◽

Nozomu TOGAWA ◽

Masao YANAGISAWA ◽

Tatsuo OHTSUKI

Keyword(s):

High Level Synthesis ◽

High Level

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A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e100.a.1439 ◽

2017 ◽

Vol E100.A (7) ◽

pp. 1439-1451

Author(s):

Koki IGAWA ◽

Masao YANAGISAWA ◽

Nozomu TOGAWA

Keyword(s):

High Level Synthesis ◽

Synthesis Algorithm ◽

Body Biasing ◽

High Level ◽

Delay Variation

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Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e97.a.2498 ◽

2014 ◽

Vol E97.A (12) ◽

pp. 2498-2506

Author(s):

Akihiro SUDA ◽

Hideki TAKASE ◽

Kazuyoshi TAKAGI ◽

Naofumi TAKAGI

Keyword(s):

High Level Synthesis ◽

Loop Parallelization ◽

Polyhedral Optimization ◽

High Level ◽

Nested Loop

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A parallel ant colony optimization to globally optimize area in high-level synthesis. (c2011)

10.26756/th.2011.36 ◽

2011 ◽

Author(s):

David Elias Kozhaya

Keyword(s):

Ant Colony Optimization ◽

Ant Colony ◽

High Level Synthesis ◽

High Level

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Language requirements for high-level synthesis

10.3403/00837025 ◽

1996 ◽

Keyword(s):

High Level Synthesis ◽

High Level

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