Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits

2012 ◽  
Author(s):  
Wen-Pin Tu ◽  
Shih-Hsu Huang ◽  
Chun-Hua Cheng
Keyword(s):  
High Level Synthesis ◽  
Clock Skew ◽  
Clock Period ◽  
Minimum Area ◽  
Area Overhead ◽  
High Level

scholarly journals High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis

2011 ◽  
Vol 2011 ◽  
pp. 1-17 ◽  
Author(s):  
John Curreri ◽  
Greg Stitt ◽  
Alan D. George
Keyword(s):  
Timing Analysis ◽  
High Level Synthesis ◽  
Timing Constraints ◽  
Software Developers ◽  
Design Complexity ◽  
Elapsed Time ◽  
Area Overhead ◽  
Limited Support ◽  
Significant Performance ◽  
High Level

Despite significant performance and power advantages compared to microprocessors, widespread usage of FPGAs has been limited by increased design complexity. High-level synthesis (HLS) tools have reduced design complexity but provide limited support for verification, debugging, and timing analysis. Such tools generally rely on inaccurate software simulation or lengthy register-transfer-level simulations, which are unattractive to software developers. In this paper, we introduce HLS techniques that allow application designers to efficiently synthesize commonly used ANSI-C assertions into FPGA circuits, enabling verification and debugging of circuits generated from HLS tools, while executing in the actual FPGA environment. To verify that HLS-generated circuits meet execution timing constraints, we extend the in-circuit assertion support for testing of elapsed time for arbitrary regions of code. Furthermore, we generalize timing assertions to transparently provide hang detection that back annotates hang occurrences to source code. The presented techniques enable software developers to rapidly verify, debug, and analyze timing for FPGA applications, while reducing frequency by less than 3% and increasing FPGA resource utilization by 0.7% or less for several application case studies on the Altera Stratix-II EP2S180 and Stratix-III EP3SE260 using Impulse-C. The presented techniques reduced area overhead by as much as 3x and improved assertion performance by as much as 100% compared to unoptimized in-circuit assertions.

scholarly journals Architectural Power Estimation Based on Behavior Level Profiling

VLSI Design ◽  
1998 ◽  
Vol 7 (3) ◽  
pp. 255-270 ◽  
Author(s):  
Srinivas Katkoori ◽  
Ranga Vemuri
Keyword(s):  
Power Estimation ◽  
Low Power Design ◽  
High Level Synthesis ◽  
Clock Period ◽  
Component Library ◽  
Throughput Rate ◽  
Register Transfer ◽  
High Level ◽  
Short Time ◽  
The Given

High level synthesis is the process of generating register transfer (RT) level designs from behavioral specifications. High level synthesis systems have traditionally taken into account such constraints as area, clock period and throughput time. Many high level synthesis systems [1] permit generation of many alternative RT level designs meeting these constraints in a relatively short time. If it is possible to accurately estimate the power consumption of RT level designs, then a low power design from among these alternatives can be selected.In this paper, we present an accurate power estimation technique for register transfer level designs generated by high level synthesis systems. The technique has four main aspects: (1) Each RT level component used in high level synthesis is characterized for average switched capacitance per input vector. This data is stored in the RT level component library. (2) Using user-specified stimuli, the given behavioral description is simulated and event activities of various operators and carriers are measured. Then, the behavioral specification is submitted to the synthesis system and a number of alternative RTL designs meeting speed, space and throughput rate constraints are generated. (3) Event activity of each component in an RT level design is estimated using the event activities measured at the time of behavior level profiling and the structure of the RTL design itself. (4) The event activities so obtained are then used to modulate the average switched capacitances of the respective RT level components to obtain an estimate the total switched capacitance of each component.Detailed power estimation procedures for the three different parts of RTL designs, namely, data path, controller and interconnect are presented. Experimental results obtained from a variety of designs show that the power estimates are within 3%–10% of the actual power measured by simulating the transistor level designs extracted from mask layouts.

Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

2009 ◽  
Vol E92-A (12) ◽  
pp. 3169-3179 ◽  
Author(s):  
Akira OHCHI ◽  
Nozomu TOGAWA ◽  
Masao YANAGISAWA ◽  
Tatsuo OHTSUKI
Keyword(s):  
High Level Synthesis ◽  
High Level
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