An Efficient LDPC Decoder Architecture with a High-Performance Decoding Algorithm

2010 ◽  
Vol E93-B (11) ◽  
pp. 2980-2989
Author(s):  
Jui-Hui HUNG ◽  
Sau-Gee CHEN
Keyword(s):  
High Performance ◽  
Decoding Algorithm ◽  
Ldpc Decoder ◽  
Decoder Architecture

scholarly journals Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 516
Author(s):  
Tram Thi Bao Nguyen ◽  
Tuy Nguyen Tan ◽  
Hanho Lee
Keyword(s):  
Wireless Communication ◽  
High Throughput ◽  
Low Complexity ◽  
Ldpc Decoder ◽  
Processor Architectures ◽  
New Radio ◽  
Decoder Architecture ◽  
Check Node ◽  
Information Update ◽  
Wireless Standards

This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.

A high performance MQ decoder architecture in JPEG2000

2014 ◽  
Author(s):  
Layla Horrigue ◽  
Taoufik Saidani ◽  
Refka Ghodhbane ◽  
Mohamed Atri
Keyword(s):  
High Performance ◽  
Decoder Architecture

scholarly journals An Efficient High-Rate Non-Binary LDPC Decoder Architecture With Early Termination

IEEE Access ◽  
2019 ◽  
Vol 7 ◽  
pp. 20302-20315 ◽  
Author(s):  
Mao-Ruei Li ◽  
Wei-Xiang Chu ◽  
Huang-Chang Lee ◽  
Yeong-Luh Ueng
Keyword(s):  
Early Termination ◽  
High Rate ◽  
Ldpc Decoder ◽  
Decoder Architecture
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