A new simplified RRWBF decoding algorithm for LDPC decoder in CMMB

2014 ◽  
Author(s):  
Xiangran Sun ◽  
Yunyun Wei
Keyword(s):  
Decoding Algorithm ◽  
Ldpc Decoder

scholarly journals An efficient multi-standard QC-LDPC decoder based on the row-layered decoding algorithm

2015 ◽  
Vol 12 (13) ◽  
pp. 20150356-20150356
Author(s):  
Song Guo ◽  
Yong Dou ◽  
Yuanwu Lei ◽  
Rongchun Li ◽  
Yu Li
Keyword(s):  
Decoding Algorithm ◽  
Ldpc Decoder ◽  
Layered Decoding

Implementation of QC-LDPC Decoder Based on FPGA for FSO System

2014 ◽  
Vol 668-669 ◽  
pp. 1269-1272
Author(s):  
Yan Guo Qiong ◽  
Zhou Mao Hua
Keyword(s):  
High Speed ◽  
Functional Unit ◽  
Hardware Description Language ◽  
Coding Gain ◽  
Decoding Algorithm ◽  
Description Language ◽  
Matlab Software ◽  
Decoding Complexity ◽  
Ldpc Decoder ◽  
Hardware Description

QC-LDPC can bring a higher coding gain to the FSO system, but the complexity of the decoding algorithm restricted its application in high-speed FSO system.In this paper, it adopts an improved Modified Min-sum Algorithm (MMSA) to reduce the decoding complexity and save decoding time. In this paper, the author programs the decoder with VHDL Hardware Description Language and analyzes the static time of the design with Synplify Pro and QuartusII to verify the correctness. Moreover, each functional unit is downloaded to the EP3C16Q240C8 chip produced by ALTERA Company and encapsulated into the IP core. Finally, we used MATLAB software to build the FSO system for testing decoder performance. The results show that the QC-LDPC decoder based on FPGA has higher reliability in FSO system.

FPGA Implementation of High-Speed Memory Efficient Quasi-Cyclic LDPC Decoder

2013 ◽  
Vol 380-384 ◽  
pp. 3328-3331
Author(s):  
Jian Bing Han ◽  
Chen He ◽  
Ran Zhen
Keyword(s):  
High Speed ◽  
Optimization Design ◽  
Fpga Implementation ◽  
Turbo Decoding ◽  
Decoding Algorithm ◽  
Frame Size ◽  
Ldpc Decoder ◽  
Code Structure ◽  
Structure Algorithm ◽  
Memory Efficient

This paper introduces a new kind of decoder structure for FPGA implementation of high-speed memory efficient quasi-cyclic LDPC (QC-LDPC) decoder. The code structure, algorithm and hardware structure all adopt optimization design. The decoder adopts modified Turbo decoding algorithm and achieves a decoding throughput of 223 Mbps and frame size of 3,200 bits. The Xilinx Virtex-4 chip used by the decoder only takes up 71 KB memory and makes it exceeds other decoders in aspects of throughput and memory for FPGA implementation.

FPGA-Based Improved Decoding Algorithm of LDPC Codes

2014 ◽  
Vol 519-520 ◽  
pp. 995-999
Author(s):  
Qian Hua Zhang ◽  
Jian Wu Zhang ◽  
Jian Rong Bao
Keyword(s):  
Computational Complexity ◽  
Ldpc Codes ◽  
Bp Algorithm ◽  
Floating Point ◽  
Data Systems ◽  
Deep Space ◽  
Decoding Algorithm ◽  
Signal To Noise ◽  
Ldpc Decoder ◽  
Space Data

In this paper, a low-complexity LDPC decoder structure was proposed by optimizing the confidence propagation algorithm based on the deep space standard LDPC codes developed by the Consultative Committee for Space Data Systems (CCSDS). With the improved decoding algorithm, the structure made full use of the quasi-cyclic structure to reduce the variables in the decoder and the storage unit use for the index position of the check nodes, which saves the hardware resources greatly. Furthermore, the updating of the check nodes takes advantages of the information iterative structure of the JPL-LDPC decoder, which can reduce the computational complexity. By improving the searching methods, the computational complexity and the difficulty in FPGA implementation were reduced. The decoding performance of the decoder is close to that of the floating-point BP algorithm, which can be widely used in deep space communication with low signal-to-noise ratio.performance close to a floating-point the BP algorithm performance, can be widely used in deep space communications suitable for low signal-to-noise ratio transmission.

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