scholarly journals A memory size reduction method of pipelined IFFT processor for OFDM systems

2011 ◽  
Vol 8 (19) ◽  
pp. 1627-1632
Author(s):  
In-Gul Jang ◽  
Kyung-Ju Cho
Keyword(s):  
Reduction Method ◽  
Size Reduction ◽  
Ofdm Systems ◽  
Memory Size

Fabrication of Silicon Nanowires by Electron Beam Lithography and Thermal Oxidation Size Reduction Method

2013 ◽  
Vol 832 ◽  
pp. 415-418 ◽  
Author(s):  
Mohammad Nuzaihan Md Nor ◽  
Uda Hashim ◽  
Taib Nazwa ◽  
Tijjani Adam
Keyword(s):  
Electron Beam ◽  
Thermal Oxidation ◽  
Silicon Nanowires ◽  
Electron Beam Lithography ◽  
Reduction Method ◽  
Size Reduction ◽  
Simple Method ◽  
Force Microscopy ◽  
Initial Silicon ◽  
20 Nm

A simple method for the fabrication of silicon nanowires using Electron Beam Lithography (EBL) combined with thermal oxidation size reduction method is presented. EBL is used to define the initial silicon nanowires of dimensions approximately 100 nm. Size-reduction method is employed for reaching true nanoscale of dimensions approximately 20 nm. Dry oxidation of silicon is well investigated process for self-limited size-reduction of silicon nanowires. In this paper, successful size reduction of silicon nanowires is presented and surface topography characterizations using Atomic Force Microscopy (AFM) are reported.

Sign in / Sign up

Export Citation Format

Share Document