scholarly journals An ultra low-power low-voltage switched-comparator successive approximation analog to digital converter

2009 ◽  
Vol 6 (15) ◽  
pp. 1098-1104 ◽  
Author(s):  
Ali Valaee ◽  
Mohammad Maymandi-nejad
Keyword(s):  
Low Power ◽  
Successive Approximation ◽  
Low Voltage ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Ultra Low Power ◽  
Analog To Digital

A Successive Approximation Register Analog to Digital Converter for Low Power Applications

2020 ◽  
Vol 17 (1) ◽  
pp. 451-455
Author(s):  
Yahya Mohammed Ali Al-Naamani ◽  
K. Lokesh Krishna ◽  
A. M. Guna Sekhar
Keyword(s):  
Low Power ◽  
Successive Approximation ◽  
Research Work ◽  
Implantable Devices ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Ultra Low Power ◽  
Silicon Area ◽  
Analog To Digital ◽  
Successive Approximation Register

In recent years and continuing, widespread research work is carried out on medical implantable devices placed inside the human body. The essential and vital electronic circuit in implantable devices is the Analog to Digital Converter (ADC). The essential requirements in these applications such as long battery life-time, low power consumption and less die area poses a stringent requirement in designing and fabricating an ultra-low power ADCs. Among the diverse converter architectures existing, Successive Approximation Register (SAR) type converter architecture has shown better capabilities in terms of ultra-low power operation, medium resolution, less form factor and less silicon area. In this described paper a novel power effective, better resolution SAR type ADC to be used for biomedical related applications. The proposed work consists of capacitive type Digital to Analog Converter (DAC) based on charge distribution, a CMOS comparator, and SAR logic implemented using D-flip-flops. The different blocks of SAR architecture are simulated using EDA tools in CMOS 180 nm N-well process operated at VDD = 1.5 V voltage (VDD). The circuit is measured under various input frequencies with a sampling speed of 50 MHz and it consumes 22.6 μW. The proposed ADC technology shows SNDR of 48.6 dB and occupies a circuit area of 0.11 mm2 and the measured INL and DNL is calculated to be fewer than 0.54 LSB and 0.45 LSB respectively.

Sign in / Sign up

Export Citation Format

Share Document