scholarly journals A novel highly reliable and low-power radiation hardened SRAM bit-cell design

2018 ◽  
Vol 15 (3) ◽  
pp. 20171129-20171129 ◽  
Author(s):  
Dianpeng Lin ◽  
Yiran Xu ◽  
Xiaonian Liu ◽  
Wenyi Zhu ◽  
Lihua Dai ◽  
...  
Keyword(s):  
Low Power ◽  
Cell Design ◽  
Radiation Hardened ◽  
Power Radiation

LOW POWER RADIATION HARDENED SRAM CELLS

2020 ◽  
Vol 8 (2) ◽  
pp. 22
Author(s):  
V. SEETHA ◽  
P. DEEPA ◽  
◽  
Keyword(s):  
Low Power ◽  
Radiation Hardened ◽  
Power Radiation

Ultra-Low Power Radiation Hardened by Design Memory Circuits

2007 ◽  
Vol 54 (6) ◽  
pp. 2004-2011 ◽  
Author(s):  
Tai-Hua Chen ◽  
Jinhui Chen ◽  
Lawrence T. Clark ◽  
Jonathan E. Knudsen ◽  
Giby Samson
Keyword(s):  
Low Power ◽  
Ultra Low Power ◽  
Memory Circuits ◽  
Radiation Hardened ◽  
Radiation Hardened By Design ◽  
Power Radiation

scholarly journals A wrap-gate CNT-MOSFET based SRAM bit-cell with asymmetrical ground gating and built-in read-assist schemes for limited-energy environments application

2021 ◽  
Author(s):  
Abdolreza Darabi ◽  
Mohammad Reza Salehi ◽  
Ebrahim Abiri
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Data Transfer ◽  
High Reliability ◽  
Cell Structure ◽  
Impact Resistance ◽  
Single Node ◽  
Limited Energy ◽  
Radiation Hardened ◽  
Power Radiation

Abstract Today, designing low-power single-bit SRAM structures with the ability to operate regularly at low supply voltages and with high immunity against standard radiation particles impact is challenging for designers. In the present article, a novel design of a low-power radiation-hardened single-ended SRAM bit-cell (UPRHSE) based on gate-diffusion input (GDI) method using gate-all-around carbon nano-tube (CNT) MOSFETs (GAA CNT-MOSFETs) along with dual-chirality/multiple-diameter technique for CNTs with an asymmetric virtual ground gating and built-in read-assist schemes with inherent single-node event upset (SEU) preventive and self-correction capabilities and a high degree of robustness against multiple-node event upsets (MEUs) in the presence of more consumption area storage has been proposed. In order to investigate single/double upset injection circuit model using the structure of the T-connected pseudo resistors (TPRs) has been proposed. Also, based on the analytical-compact model, an equation for calculating the data-retention voltage (VDR) metric for the suggested bit-cell structure and an algorithm for facile estimate of VDR for other bit-cell architectures is presented. The results of extensive Monte-Carlo (MC) simulations to evaluate the proposed bit-cell indicate larger noise margins, acceptable yield, less sensitivity to process, voltage and temperature (PVT) variations, higher critical charge and consequence more robustness to soft errors with high reliability of data storage in standby mode in the presence of voltage conditions lower than the nominal power supply, and better results in other comprehensive figure of merits (FoMs) criteria compared to nanotechnology-based state-of-the-art radiation-hardened (rad-hard) bit-cell circuits with the same number of transistors in the 16 nm technology node. So, the proposed UPRHSE design can be a reasonable choice for applications that demands high stability, impact resistance to radiation particles and extremely low power in a radiation abundant environment with limited-energy sources. Finally, in order to use the suggested UPRHSE bit-cell in a real application with secure data transfer approach, the suggested structure is employed for storing. The results show the better performance of UPRHSE in terms of other comprehensive FoMs based on PSNR and MSSIM metric to evaluate the appropriate accuracy in pixel-by-pixel image compared to other well-known counterpart designs.

A low-power, radiation-hardened, CAN-interface for system-on-chip space applications

2012 ◽  
Vol 3 (3-4) ◽  
pp. 89-100
Author(s):  
Georgios Pouiklis ◽  
George Kottaras ◽  
Athanasios Psomoulis ◽  
Emmanuel Sarris ◽  
Nikolaos Stamatopoulos
Keyword(s):  
Low Power ◽  
System On Chip ◽  
Space Applications ◽  
Radiation Hardened ◽  
On Chip ◽  
Power Radiation

A Low-Power Radiation-Hardened Flip-Flop with Stacked Transistors in a 65 nm FDSOI Process

2018 ◽  
Vol E101.C (4) ◽  
pp. 273-280 ◽  
Author(s):  
Haruki MARUOKA ◽  
Masashi HIFUMI ◽  
Jun FURUTA ◽  
Kazutoshi KOBAYASHI
Keyword(s):  
Low Power ◽  
Flip Flop ◽  
Radiation Hardened ◽  
Power Radiation
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