Design of 1-bit Full Adder using output wired CMOS Inverter based Threshold Gate

2020 ◽  
Vol 1 (2) ◽  
Keyword(s):  
Full Adder ◽  
Cmos Inverter ◽  
Threshold Gate

scholarly journals Design and Implementation of a Low Power Ternary Full Adder

VLSI Design ◽  
1996 ◽  
Vol 4 (1) ◽  
pp. 75-81 ◽  
Author(s):  
A. Srivastava ◽  
K. Venkatapathy
Keyword(s):  
Low Power ◽  
Dynamic Performance ◽  
Building Blocks ◽  
Full Adder ◽  
Cmos Technology ◽  
Model Parameters ◽  
Cmos Inverter ◽  
Design And Implementation ◽  
Present Design ◽  
Ternary Full Adder

In this work, the design and implementation of a low power ternary full adder are presented in CMOS technology. In a ternary full adder design, the basic building blocks, the positive ternary inverter (PTI) and negative ternary inverter (NTI) are developed using a CMOS inverter and pass transistors. In designs of PTI and NTI, W/L ratios of transistors have been varied for their optimum performance. The ternary full adder and its building blocks have been simulated with SPICE 2G.6 using the MOSIS model parameters. The rise and fall times of PTI show an improvement by a factor of 14 and 4, respectively, and that of the NTI by a factor of nearly 4 and 17, respectively over that of earlier designs implemented in depletion-enhancement CMOS (DECMOS) technology. The noise margins improve by a factor of nearly 2 in PTI and NTI, respectively.The ternary full adder has been fabricated in MOSIS two micron n-well CMOS technology. The full adder and its building blocks, NTI and PTI have been tested experimentally for static and dynamic performance, compared with the SPICE simulated behavior, and close agreement is observed.The ternary-valued logic circuits designed in the present work which do not use depletion mode MOSFETS perform better than that implemented earlier in DECMOS technology. The present design is fully compatible with the current CMOS technology, uses fewer components and dissipates power in the microwatt range.

scholarly journals Transistor sizing of CMOS VLSI Circuits in Deep Submicron Technology

2019 ◽  
Vol 8 (11S2) ◽  
pp. 15-29
Keyword(s):  
Full Adder ◽  
Deep Submicron ◽  
Vlsi Circuits ◽  
Total Power ◽  
Cmos Inverter ◽  
Transistor Sizing ◽  
Cmos Vlsi

In Very-huge scale reconciliation (VLSI) application zone, postponement and power are the significant variables for any advanced circuits. Its observed that the as CMOS Inverter Transistor Size decreases from 1µm to 120nm, power reduced from 3.331 to 2.644 (µW) and delay reduced from 5.026 to 22.66 (pS). It is observed that the table 4 as 28T Full Adder Circuit Voltage Scale decreases from 5 V to 1 V, Total power reduced from 63150 to 2262 (nW) and delay reduced from 39.93 to 38.52 (nS) in 180nm technology. It is observed that the table 6 as 28T Full Adder Circuit Voltage Scale decreases from 2 V to 0.8 V, Total power reduced from 21.39 to 2.916 (µW) and delay reduced from 4.939 to 4.74 (nS) in 90nm technology. It is observed that the table 8 as 28T Full Adder Circuit Voltage Scale decreases from 1.5 V to 0.7 V, Total power reduced from 8.98 to 1.713 (µW) and delay reduced from 4.963 to 4.581 (nS) in 45nm technology.

A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter

2009 ◽  
Vol 40 (10) ◽  
pp. 1441-1448 ◽  
Author(s):  
K. Navi ◽  
V. Foroutan ◽  
M. Rahimi Azghadi ◽  
M. Maeen ◽  
M. Ebrahimpour ◽  
...  
Keyword(s):  
Low Power ◽  
Full Adder ◽  
New Technique ◽  
Cmos Inverter

A POWER EFFICIENT NMOS BASED FULL ADDER USING PTL LOGIC

2017 ◽  
Vol 5 (4) ◽  
pp. 15
Author(s):  
ISWARIYA S. ◽  
RAJA M. VILASINI ◽  
◽  
Keyword(s):  
Full Adder ◽  
Power Efficient

Full adder design based on hybrid logic of M4 structure

2014 ◽  
Vol 31 (5) ◽  
pp. 479
Author(s):  
Yinshui Xia ◽  
Shiheng Wang ◽  
Libo Qian
Keyword(s):  
Full Adder ◽  
Hybrid Logic

Suppression of Timing Variations due to Random Dopant Fluctuation by Back-Gate Bias in a Nanometer CMOS Inverter

2020 ◽  
Vol 13 ◽  
Author(s):  
Kai Zhang ◽  
Weifeng Lü ◽  
Peng Si ◽  
Zhifeng Zhao ◽  
Tianyu Yu
Keyword(s):  
Monte Carlo ◽  
Integrated Circuits ◽  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Cmos Inverter ◽  
Back Gate ◽  
Random Dopant Fluctuation ◽  
Random Dopant

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits. Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology. Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG. Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover, that they are also insensitive to channel doping with back-gate bias. Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.

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