scholarly journals The object-oriented design of a hardware description language analyser for the DIADES silicon compiler system

2000 ◽  
Author(s):  
Lian Yang
Keyword(s):  
Object Oriented ◽  
Hardware Description Language ◽  
Description Language ◽  
Object Oriented Design ◽  
Silicon Compiler ◽  
Hardware Description ◽  
Compiler System

Efficient Conversion Technique from Redundant Binary to NonRedundant Binary Representation

2017 ◽  
Vol 26 (09) ◽  
pp. 1750135 ◽  
Author(s):  
Ranjan Kumar Barik ◽  
Manoranjan Pradhan ◽  
Rutuparna Panda
Keyword(s):  
Final Stage ◽  
Hardware Description Language ◽  
Binary Representation ◽  
Description Language ◽  
Power Product ◽  
Efficient Conversion ◽  
Look Ahead ◽  
Hardware Description ◽  
Sign Extension ◽  
Cadence Tool

Redundant Binary (RB) to Two’s Complement (TC) converter offers nonredundant representation. However, the sign bit of TC representation has to be handled using nonstandard hardware blocks. The concept of Inverted encoding of negative weighted bits (IEN) eliminates the need of sign extension and offers design only using predefined hardware blocks. NonRedundant Binary (NRB) representation refers to both conventional and IEN representations. The NRB representation is also useful considering problem related to shifting in Carry Save (CS) representation of a RB number. In this paper, we have proposed two new conversion circuits for RB to NRB representation. The proposed circuits of the RB to NRB converter are coded in Verilog Hardware Description language (HDL) and synthesized using the Encounter(R) RTL Compiler RC13.10 v13.10-s006_1 of Cadence tool considering ASIC platform. Considering 64 bits’ operand, the delay power product performances of proposed one-bit and two-bit computations offer improvement of almost 29.9% and 47%, respectively as compared to Carry-Look-Ahead (CLA). The proposed one-bit converter is also applied in the final stage of the Modified Redundant Binary Adder (MRBA). The 32-bit MRBA offers a delay improvement of 7.87% replacing conventional converter with proposed one-bit converter in same FPGA 4vfx12sf363-12 device.

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