The band alignment problem at the Si-high-k dielectric interface

2003 ◽  
Vol 786 ◽  
Author(s):  
A.A. Demkov ◽  
L.R.C. Fonseca ◽  
J. Tomfohr ◽  
O.F. Sankey
Keyword(s):  
Gate Dielectrics ◽  
Local Density ◽  
Band Alignment ◽  
Charge Neutrality ◽  
Model Calculations ◽  
High K ◽  
Band Position ◽  
Alignment Problem ◽  
Consistent Picture ◽  
High K Dielectric

ABSTRACTWe investigate the use of the complex band structure of high-k gate dielectrics to estimate their charge neutrality levels, and compute band offsets to Si. Results of these model calculations are then compared to those obtained with direct electronic structure methods and available experiment. It appears that charge neutrality levels thus obtained indeed provide a consistent picture. However, the uncertainty in the conduction band position inherent in the local density approximation may render the theory inadequate for the engineering support. Despite this limitation, linear re-scaling of the charge neutrality levels based on the experimental band gaps has shown excellent agreement with experimental data.

Band alignment of high-k dielectric on SiO2/Si stack

2012 ◽  
Author(s):  
Jinjuan Xiang ◽  
Xiaolei Wang ◽  
Tingting Li ◽  
Chao Zhao ◽  
Wenwu Wang ◽  
...  
Keyword(s):  
Band Alignment ◽  
High K ◽  
High K Dielectric

X-ray photoelectron spectroscopy energy band alignment of spin-on CoTiO3 high-k dielectric prepared by sol-gel spin coating method

2008 ◽  
Vol 93 (9) ◽  
pp. 092907 ◽  
Author(s):  
Kuo-Hsing Kao ◽  
Shiow-Huey Chuang ◽  
Woei-Cherng Wu ◽  
Tien-Sheng Chao ◽  
Jian-Hao Chen ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Spin Coating ◽  
Energy Band ◽  
Sol Gel ◽  
Band Alignment ◽  
X Ray ◽  
Spin Coating Method ◽  
High K ◽  
Coating Method ◽  
High K Dielectric

Effective Dielectric Thickness Scaling for High-K Gate Dielectric Mosfets

2002 ◽  
Vol 716 ◽  
Author(s):  
Krishna Kumar Bhuwalka ◽  
Nihar R. Mohapatra ◽  
Siva G. Narendra ◽  
V Ramgopal Rao
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Channel Length ◽  
Short Channel ◽  
Dielectric Thickness ◽  
High K ◽  
Fringing Field ◽  
High K Dielectric ◽  
Physical Thickness

AbstractIt has been shown recently that the short channel performance worsens for high-K dielectric MOSFETs as the physical thickness to the channel length ratio increases, even when the effective oxide thickness (EOT) is kept identical to that of SiO2. In this work we have systematically evaluated the effective dielectric thickness for different Kgate to achieve targeted threshold voltage (Vt), drain-induced barrier lowering (DIBL) and Ion/Ioff ratio for different technology generations down to 50 nm using 2-Dimensional process and device simulations. Our results clearly show that the oxide thickness scaling for high-K gate dielectrics and SiO2 follow different trends and the fringing field effects must be taken into account for estimation of effective dielectric thickness when SiO2 is replaced by a high-K dielectric.

Chemical beam deposition of high-k gate dielectrics on III-V semiconductors: TiO2 on In0.53Ga0.47As

2009 ◽  
Vol 1155 ◽  
Author(s):  
Roman Engel-Herbert ◽  
Yoontae Hwang ◽  
James LeBeau ◽  
Yan Zheng ◽  
Susanne Stemmer
Keyword(s):  
Photoelectron Spectroscopy ◽  
Gate Dielectrics ◽  
Titanium Isopropoxide ◽  
Band Alignment ◽  
Oxide Semiconductor ◽  
Leakage Currents ◽  
Transmission Electron ◽  
High K ◽  
Abrupt Interface ◽  
Beam Deposition

AbstractWe report on the growth of high-permittivity (k) TiO2 thin films on In0.53Ga0.47As channels by chemical beam deposition with titanium isopropoxide as the source. The films grew in a reaction-limited regime with smooth surfaces. High-resolution transmission electron microscopy showed an atomically abrupt interface with the In0.53Ga0.47As channel that indicated that this interface is thermally stable. Measurements of the leakage currents using metal-oxide-semiconductor capacitors with Pt top electrodes revealed asymmetric characteristics with respect to the bias polarity, suggesting an unfavorable band alignment for CMOS applications. X-ray photoelectron spectroscopy was used to determine the TiO2/In0.53Ga0.47As band offsets. A valence band offset of 2.5 ± 0.1 eV was measured.

Sub-20nm Device Voltage-Sensitive SRAM Characterization and Failure Analysis

2018 ◽  
Author(s):  
Seng Nguon Ting ◽  
Hsien-Ching Lo ◽  
Donald Nedeau ◽  
Aaron Sinnott ◽  
Felix Beaudoin
Keyword(s):  
Failure Analysis ◽  
High Performance ◽  
Yield Loss ◽  
Technology Development ◽  
High Density ◽  
High K ◽  
Yield Learning ◽  
Oxide Deposition ◽  
Edge Profile ◽  
High K Dielectric

Abstract With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.

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