Oxide-Semiconductor Interface Characterization Using Kelvin Probe-AFM In Combination With Corona-Charge Deposition

2003 ◽  
Vol 786 ◽  
Author(s):  
Bert Lägel ◽  
Maria D. Ayala ◽  
Elena Oborina ◽  
Rudy Schlaf
Keyword(s):  
Integrated Circuits ◽  
Oxide Thickness ◽  
Oxide Semiconductor ◽  
Lateral Resolution ◽  
Surface Barrier ◽  
Screening Methods ◽  
Kelvin Probe ◽  
Semiconductor Interface ◽  
Charge Deposition ◽  
Corona Charge

ABSTRACTCorona charge deposition methods in combination with spatially resolved surface potential measurements have become a standard tool for Si oxide quality monitoring. Based on this technique oxide-semiconductor interface parameters such as surface barrier height, oxide thickness and oxide charge density can now be monitored in-line with commercially available devices. The ongoing downscaling of integrated circuits into the sub-100 nm regime makes the development of high resolution oxide screening methods increasingly important.However, currently available commercial devices are limited in their spatial resolution since they employ the traditional vibrating Kelvin probe technique, restricting their lateral resolution to several μm. In order to increase the lateral resolution of this measurement method we have combined the corona-charge deposition technique with Kelvin Probe AFM. We present initial results of this novel measurement technique and demonstrate its feasibility by measurements on lithographically prepared oxide patterns on Si wafers with different oxide thicknesses.

Growth of Thin SiO2 bY “SPIKE” Rapid Thermal Oxidation

1999 ◽  
Vol 567 ◽  
Author(s):  
A. T. Fiory
Keyword(s):  
Film Thickness ◽  
Physical Properties ◽  
Thermal Oxidation ◽  
Atmospheric Pressure ◽  
Oxide Thickness ◽  
Peak Temperature ◽  
Surface Photovoltage ◽  
Kelvin Probe ◽  
Power Prior ◽  
Corona Charge

ABSTRACTWafers prepared with HF and RCA cleaning were oxidized at atmospheric pressure O2 with an incandescent-lamp processor using temperature ramping at rates up to 150°C/s for heating and 80°C/s for cooling. The minimum oxidation time obtained by the “spike” method of turning off lamp power prior to reaching a desired peak temperature is effectively 2s. Film thickness for spike oxidation ranges from about 1.6 nm for peak temperature of 1000°C to about 2.2 nm for peak temperature of 1100°C. Activation energies of 2.5 eV are determined for 1.5 – 4 nm films. Films grown for varied times and temperatures to produce equal oxide thickness, as measured by ellipsometry, show nearly equivalent physical properties in measurements by corona-charge and Kelvin probe surface photovoltage techniques.

n-wells voltage contrast imaging with a Focused Ion Beam

2003 ◽  
Vol 792 ◽  
Author(s):  
Erwan Le Roy ◽  
Mark Thompson
Keyword(s):  
Integrated Circuits ◽  
Focused Ion Beam ◽  
Silicon Oxide ◽  
Ion Beam ◽  
Oxide Thickness ◽  
Oxide Semiconductor ◽  
Contrast Imaging ◽  
Oxide Interface ◽  
Capacitive Properties ◽  
Capacitive Effect

Using a focused ion beam (FIB), secondary electron (SE) imaging of n-wells under oxide from the backside of thinned integrated circuits without electrical bias was accomplished. From the backside, the n-wells were initially observed at a remaining silicon thickness ∼4.5μm, which correlates to the actual implant depth where n and p carrier concentrations are equal. When the wells were FIB imaged, contrast appeared dark relative to the p substrate. During deposition of the oxide film, the n-well brightness changed from dark relative to the p-substrate, to bright. It appears that initially during this deposition step the interaction volume of the beam reached the silicon/oxide interface to create tunneling electrons. This phenomenon dominated the capacitive effect. Then as the film thickness increased the capacitive effect prevailed. The imaging structure is analogous to a Metal-Oxide-Semiconductor (MOS) capacitor. The n- and p-MOS capacitive properties yielded a permanent imaging contrast. At an optimized oxide thickness (130nm), the n-wells appear white relative to the p-substrate with a contrast up to 85% {(Ip-substrate − In-wells)/(Ipsubstrate + In-wells)}.

Suppression of Timing Variations due to Random Dopant Fluctuation by Back-Gate Bias in a Nanometer CMOS Inverter

2020 ◽  
Vol 13 ◽  
Author(s):  
Kai Zhang ◽  
Weifeng Lü ◽  
Peng Si ◽  
Zhifeng Zhao ◽  
Tianyu Yu
Keyword(s):  
Monte Carlo ◽  
Integrated Circuits ◽  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Cmos Inverter ◽  
Back Gate ◽  
Random Dopant Fluctuation ◽  
Random Dopant

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits. Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology. Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG. Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover, that they are also insensitive to channel doping with back-gate bias. Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.

scholarly journals Comparative Study ofSiO2,Al2O3, and BeO Ultrathin Interfacial Barrier Layers in Si Metal-Oxide-Semiconductor Devices

2012 ◽  
Vol 2012 ◽  
pp. 1-7 ◽  
Author(s):  
J. H. Yum ◽  
J. Oh ◽  
Todd. W. Hudnall ◽  
C. W. Bielawski ◽  
G. Bersuker ◽  
...  
Keyword(s):  
Metal Oxide ◽  
High Performance ◽  
Field Effect Transistors ◽  
Beryllium Oxide ◽  
Atomic Layer ◽  
Oxide Thickness ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Flat Band ◽  
Effective Electron

In a previous study, we have demonstrated that beryllium oxide (BeO) film grown by atomic layer deposition (ALD) on Si and III-V MOS devices has excellent electrical and physical characteristics. In this paper, we compare the electrical characteristics of inserting an ultrathin interfacial barrier layer such as SiO2, Al2O3, or BeO between the HfO2gate dielectric and Si substrate in metal oxide semiconductor capacitors (MOSCAPs) and n-channel inversion type metal oxide semiconductor field effect transistors (MOSFETs). Si MOSCAPs and MOSFETs with a BeO/HfO2gate stack exhibited high performance and reliability characteristics, including a 34% improvement in drive current, slightly better reduction in subthreshold swing, 42% increase in effective electron mobility at an electric field of 1 MV/cm, slightly low equivalent oxide thickness, less stress-induced flat-band voltage shift, less stress induced leakage current, and less interface charge.

A Comparison of Tunneling Through Thin Oxide Layers on Step-free and Normal Si Surfaces

2002 ◽  
Vol 747 ◽  
Author(s):  
Antonio C. Oliver ◽  
Jack M. Blakely
Keyword(s):  
Thermal Oxidation ◽  
Oxide Thickness ◽  
Oxide Semiconductor ◽  
Electrical Performance ◽  
Oxide Surface ◽  
Interface Morphology ◽  
Device Structure ◽  
Atomic Steps ◽  
Surface And Interface ◽  
Step Density

ABSTRACTSurface and interface morphology may play an important role in the electrical performance of metal-oxide-semiconductor (MOS) devices with small characteristic dimensions. In previous work we showed how steps on the silicon surface influence the Si-SiO2 interface morphology and the outer oxide surface morphology following thermal oxidation [1]. The Si-SiO2 interface morphology is largely determined by the starting silicon substrate step distribution and atomic steps at the Si surface cause an inherent variation in oxide thickness after thermal oxidation. In the present study we report how roughness caused by increased interfacial step density may affect the electronic tunneling characteristics of an MOS device structure. To determine the extent to which the step morphology plays a role in the tunneling behavior of such devices, similar arrays of capacitors were fabricated on both Si surfaces with reduced step density and surfaces which had not undergone any special surface step removal treatment. The leakage currents due to tunneling for the two types of capacitors were measured and compared. Atomic steps cause an effective decrease in oxide thickness in those capacitors without reduced step density and this leads to increased leakage current.

Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits

2014 ◽  
Vol 13 (02) ◽  
pp. 1450012 ◽  
Author(s):  
Manorama Chauhan ◽  
Ravindra Singh Kushwah ◽  
Pavan Shrivastava ◽  
Shyam Akashe
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Low Power ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
State Dependency ◽  
Low Leakage

In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.

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