Short Channel Length Planar Tft's Using Amorphous Silicon Alloys

1986 ◽  
Vol 70 ◽  
Author(s):  
M. Yang ◽  
Z. Yaniv ◽  
M. Vijan ◽  
V. Cannella

ABSTRACTThere is a rapid growth of interest in the application of amorphous silicon alloy thin film devices to large area microelectronic circuits. Increased current levels are a constant goal since gains in device current result in proportional gains in power and speed. Mobility limitations in amorphous silicon thin film transistors have directed interest toward short conduction channel devices to achieve higher current levels; furthermore, compatibility with large area processing makes photolithography with 10μm feature size very attractive. Consequently, innovative techniques, which define channel lengths by processing parameters rather than by mask feature size are necessary. Previous work has applied such techniques to vertical structure TFT's which define channel lengths by the vertical height of deposited layers. Here, we report on a technique which achieves short channel lengths in planar structures using etching parameters to define short channel lengths. Amorphous silicon alloy TFTs have been fabricated with channel lengths of ≈2μm which reach currents of lma. These techniques broaden the range of application of amorphous silicon alloy TFTs by providing devices capable of operating at higher currents and higher speeds.

1998 ◽  
Vol 508 ◽  
Author(s):  
P. Mei ◽  
J. B. Boyce ◽  
D. K. Fork ◽  
G. Anderson ◽  
J. Ho ◽  
...  

AbstractDistinct features of amorphous and polycrystalline silicon are attractive for large-area electronics. These features can be utilized in a hybrid structure which consists of both amorphous and polycrystalline silicon materials. For example, an extension of active matrix technology is the integration of peripheral drivers for the improvement of reliability, cost reduction and compactness of the packaging for large-area electronics. This goal can be approached by a combination of amorphous silicon pixel switches and polysilicon drivers. A monolithic fabrication process has been developed based on a simple modification of the amorphous silicon transistor process which uses selective area laser crystallization. This approach allows us to share many of the process steps involved in making both the amorphous and polysilicon devices. Another example of the hybrid device structure is a self-aligned amorphous silicon thin film transistor with polysilicon source and drain contacts. The advantages of the self-aligned transistor are reduction of the parasitic capacitance and scaling down of the device dimension. With a selective laser doping technique, self-aligned and short-channel amorphous silicon thin film transistors have been demonstrated.


1989 ◽  
Vol 149 ◽  
Author(s):  
J. G. Shaw ◽  
M. Hack

ABSTRACTWe describe a vertical amorphous silicon thin-film transistor which is easy to fabricate and has a very short channel length that is determined by deposition, not lithography. Our vertical TFTs are compatible with large-area processing techniques andd have suitable terminal characteristics for use in practical circuits. Unlike a conventional thin-film transistor, the current path is primarily parallel to the electric field created by an insulated gate electrode. A two-dimensional computer program is used to analyze these devices and guide their design and optimization. We show how to suppress excessive leakage currents and improve the saturation of the output characteristics by a novel current-blocking technique.


1984 ◽  
Vol 33 ◽  
Author(s):  
H. C. Tuan

ABSTRACTIn this paper, the amorphous silicon thin film transistor (a-Si:HTFT) technology is reviewed. Its applications to both one- and two-dimensional large-area devices are described. The issues related to the fabrication of TFT arrays on large-area substrates are also discussed.


2007 ◽  
Vol 561-565 ◽  
pp. 1165-1168 ◽  
Author(s):  
Chien Yie Tsay ◽  
Chung Kwei Lin ◽  
Hong Ming Lin ◽  
Shih Chieh Chang ◽  
Bor Chuan Chung

The TFTs array fabrication process for large-area TFT-LCD has been continuously developed for simplifying processing steps, improving performance and reducing cost in the process of mass production. In this study, the hydrogenated amorphous silicon (a-Si:H) TFTs with low resistivity electrodes , silver thin films, were prepared by using the selective deposition method that combined lift-off and electroless plated processes. This developed process can direct pattern the electrode of transistor devices without the etching process and provide ease processing steps. The as-deposited Ag films were annealed at 200 oC for 10 minutes under N2 atmosphere. The results shows that the adhesion properties can be enhanced and the resistivity has been improved from 6.0 μ,-cm, significantly decrease by 35%, of as-deposited Ag films by annealed. The thickness of Ag thin film is about 100 nm and the r. m. s roughness value is 1.54 nm. The a-Si:H TFT with Ag thin films as source and drain electrodes had a field effect mobility of 0.18 cm2/Vs, a threshold voltage of 2.65 V, and an on/off ratio of 3×104.


1984 ◽  
Vol 45 (11) ◽  
pp. 1202-1203 ◽  
Author(s):  
C. Hyun ◽  
M. S. Shur ◽  
M. Hack ◽  
Z. Yaniv ◽  
V. Cannella

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