Synthesis of High-K Titanium Oxide Thin Films Formed by Metalorganic Decomposition

1999 ◽  
Vol 606 ◽  
Author(s):  
Hisashi Fukuda ◽  
Yoshihiro Ishikawa ◽  
Seiogo Namioka ◽  
Shigeru Nomura
Keyword(s):  
Titanium Oxide ◽  
Integrated Circuit ◽  
Amorphous State ◽  
Voltage Measurement ◽  
Maximum Dielectric Constant ◽  
High K ◽  
Capacitance Voltage ◽  
Metalorganic Decomposition ◽  
Main Component ◽  
Deposited Films

AbstractTitanium oxide (TiO2) thin ftlms were formed on a Si substrate by metalorganic decomposition(MOD) at temperatures ranging from 600 to 1100°C. As-deposited films were in the amorphous state and were completely transformed after annealing at 600°C to a crystalline structure with anatase as its main component. During crystallization, a reaction between TiO2 and Si occurred at the interface, which resulted in the formation of a thin interfacial SiO2 layer. Capacitance-voltage measurement showed good dielectric properties with a maximum dielectric constant of 76 for films annealed at 700°C. For the crystallized TiO2 films, the interface trap density was 1 × 1011 cm−2 eV−1, and the leakage current was 1 × 10−8 A/cm2 at 0.2 MV/cm. The modified structure of TiO2/SiO2/Si is expected to be suitable for the dielectric layer in an integrated circuit in place of conventional SiO2 films.

Spatial and energetic distribution of border traps in the dual-layer HfO2∕SiO2 high-k gate stack by low-frequency capacitance-voltage measurement

2006 ◽  
Vol 89 (16) ◽  
pp. 162911 ◽  
Author(s):  
Wei-Hao Wu ◽  
Bing-Yue Tsui ◽  
Mao-Chieh Chen ◽  
Yong-Tian Hou ◽  
Yin Jin ◽  
...  
Keyword(s):  
Low Frequency ◽  
Voltage Measurement ◽  
Gate Stack ◽  
High K ◽  
Capacitance Voltage

Relevance of the pulsed capacitance–voltage measurement technique for the optimization of SrBi2Ta2O9/high-k stack combination to be used in FeFET devices

2006 ◽  
Vol 83 (11-12) ◽  
pp. 2564-2569 ◽  
Author(s):  
Z. Xu ◽  
L. Goux ◽  
B. Kaczer ◽  
H. Vander Meeren ◽  
D.J. Wouters ◽  
...  
Keyword(s):  
Measurement Technique ◽  
Voltage Measurement ◽  
High K ◽  
Capacitance Voltage

scholarly journals Coverage Layout Design Rules and Insertion Utilities for CMP-Related Processes

2020 ◽  
Vol 11 (1) ◽  
pp. 2
Author(s):  
Eitan N. Shauly ◽  
Sagee Rosenthal
Keyword(s):  
Integrated Circuit ◽  
Thermal Effects ◽  
Process Integration ◽  
Proximity Effects ◽  
Published Data ◽  
Metal Gate ◽  
Comprehensive Description ◽  
Advanced Technologies ◽  
High K ◽  
Rf Devices

The continuous scaling needed for higher density and better performance has introduced some new challenges to the planarity processes. This has resulted in new definitions of the layout coverage rules developed by the foundry and provided to the designers. In advanced technologies, the set of rules considers both the global and the local coverage of the front-end-of line (FEOL) dielectric layers, to the back-end-of-line (BEOL) Cu layers and Al layers, to support high-k/Metal Gate process integration. For advance technologies, a new set of rules for dummy feature insertion was developed by the integrated circuit (IC) manufacturers in order to fulfill coverage limits. New models and utilities for fill insertion were developed, taking into consideration the design coverage, thermal effects, sensitive signal line, critical analog and RF devices like inductors, and double patterning requirements, among others. To minimize proximity effects, cell insertion was also introduced. This review is based on published data from leading IC manufacturers with a careful integration of new experimental data accumulated by the authors. We aim to present a typical foundry perspective. The review provides a detailed description of the chemical mechanical polishing (CMP) process and the coverage dependency, followed by a comprehensive description of coverage rules needed for dielectric, poly, and Cu layers used in advanced technologies. Coverage rules verification data are then presented. RF-related aspects of some rules, like the size and the distance of dummy features from inductors, are discussed with additional design-for-manufacturing layout recommendations as developed by the industry.

scholarly journals Modelling of Dynamic Properties of Silicon Carbide Junction Field-Effect Transistors (JFETs)

Energies ◽  
2020 ◽  
Vol 13 (1) ◽  
pp. 187 ◽  
Author(s):  
Kamil Bargieł ◽  
Damian Bisewski ◽  
Janusz Zarębski
Keyword(s):  
Silicon Carbide ◽  
Integrated Circuit ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Dynamic Properties ◽  
Modified Model ◽  
Spice Model ◽  
Capacitance Voltage ◽  
Effect Transistor ◽  
Switching Characteristics

The paper deals with the problem of modelling and analyzing the dynamic properties of a Junction Field Effect Transistor (JFET) made of silicon carbide. An examination of the usefulness of the built-in JFET Simulation Program with Integrated Circuit Emphasis (SPICE) model was performed. A modified model of silicon carbide JFET was proposed to increase modelling accuracy. An evaluation of the accuracy of the modified model was performed by comparison of the measured and calculated capacitance–voltage characteristics as well as the switching characteristics of JFETs.

Strategic Customization of Polymeric Nanocomposites Modified by 2D Titanium Oxide Nanosheet for High‐ k and Flexible Gate Dielectrics

Small ◽  
2021 ◽  
Vol 17 (17) ◽  
pp. 2007213
Author(s):  
Moonjeong Jang ◽  
Se Yeon Park ◽  
Seong Ku Kim ◽  
Dowon Jung ◽  
Wooseok Song ◽  
...  
Keyword(s):  
Titanium Oxide ◽  
Gate Dielectrics ◽  
Polymeric Nanocomposites ◽  
High K

Semiconducting behavior of niobium-doped titanium oxide in the amorphous state

2012 ◽  
Vol 100 (14) ◽  
pp. 142103 ◽  
Author(s):  
Kyung-Chul Ok ◽  
Joseph Park ◽  
Ju Ho Lee ◽  
Byung Du Ahn ◽  
Je Hun Lee ◽  
...  
Keyword(s):  
Titanium Oxide ◽  
Amorphous State ◽  
Niobium Doped ◽  
Semiconducting Behavior

scholarly journals A New ALU Design using PNS-FCR: Static CMOS Logic for Microprocessors

2019 ◽  
Vol 8 (6S2) ◽  
pp. 876-882
Keyword(s):  
Power Consumption ◽  
Integrated Circuit ◽  
Design Methodology ◽  
Total Power ◽  
Data Path ◽  
Power Efficient ◽  
Efficient Data ◽  
Main Component ◽  
Static Logic ◽  
Important Design

Arithmetic Logic Unit (ALU) is the main component in the processors. Most important design consideration in integrated circuit is power. In all the components of ALU data path is the active one and it consumes more percent of power in the total power. In the modern microprocessors it is important to have power efficient data paths. To reduce the power consumption in microprocessors the ALU is designed using PNS-FCR static CMOS logic. In this paper static CMOS logic is used to reduce power consumption. Static technique does not need any clock. So it leads to less power consumption. For the implementation of the ALU with the PNS-FCR static logic mentor graphics tool is used. The power consumption of ALU is compared with and without using FCR. An 8-bit ALU is designed in mentor graphics with 130nm technology. The proposed design methodology gives less power consumption

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