Spatial and energetic distribution of border traps in the dual-layer HfO2∕SiO2 high-k gate stack by low-frequency capacitance-voltage measurement

2006 ◽  
Vol 89 (16) ◽  
pp. 162911 ◽  
Author(s):  
Wei-Hao Wu ◽  
Bing-Yue Tsui ◽  
Mao-Chieh Chen ◽  
Yong-Tian Hou ◽  
Yin Jin ◽  
...  
1999 ◽  
Vol 606 ◽  
Author(s):  
Hisashi Fukuda ◽  
Yoshihiro Ishikawa ◽  
Seiogo Namioka ◽  
Shigeru Nomura

AbstractTitanium oxide (TiO2) thin ftlms were formed on a Si substrate by metalorganic decomposition(MOD) at temperatures ranging from 600 to 1100°C. As-deposited films were in the amorphous state and were completely transformed after annealing at 600°C to a crystalline structure with anatase as its main component. During crystallization, a reaction between TiO2 and Si occurred at the interface, which resulted in the formation of a thin interfacial SiO2 layer. Capacitance-voltage measurement showed good dielectric properties with a maximum dielectric constant of 76 for films annealed at 700°C. For the crystallized TiO2 films, the interface trap density was 1 × 1011 cm−2 eV−1, and the leakage current was 1 × 10−8 A/cm2 at 0.2 MV/cm. The modified structure of TiO2/SiO2/Si is expected to be suitable for the dielectric layer in an integrated circuit in place of conventional SiO2 films.


2019 ◽  
Vol 2 (1) ◽  
pp. 287-300
Author(s):  
Rosa María Luna-Sánchez ◽  
Ignacio González-Martínez

2006 ◽  
Vol 83 (11-12) ◽  
pp. 2564-2569 ◽  
Author(s):  
Z. Xu ◽  
L. Goux ◽  
B. Kaczer ◽  
H. Vander Meeren ◽  
D.J. Wouters ◽  
...  

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