Study of Stress-Induced Leakage Current in Thin Oxides Stressed by Corona Charging in Air: Relationship to GOI Defects

1999 ◽  
Vol 592 ◽  
Author(s):  
M. Wilson ◽  
J. Lagowski ◽  
A. Savtchou ◽  
D. Marinskiy ◽  
L. Jastrzebski ◽  
...  

ABSTRACTCorona charging in air combined with non-contact oxide charge measurement with a contact potential difference probe provides an unique possibility for fast monitoring of electron tunneling characteristics without preparation of MOS capacitors. It has also been found tha corona charging of thin oxides in the tunneling range is very effective in generating stressinduced leakage current. In this work we demonstrate the sensitivity of the corona stressinduced leakage current magnitude to gate oxide integrity defect density. The experimenta results cover three of the most common gate oxide integrity defects, namely: 1 – the defect induced by heavy metals (Fe.Cu) at a practically important low concentration range of 1×1010 to 1×1011 atoms/cm3: 2 – the defects originating from interface roughness and 3–the defects related to crystal originated particles.At low corona stress fluence, these defects play no role in the tunneling characteristics which follow ideal Fowler-Nordheim characteristics for oxides 50Å or thicker and a contribution from a direct tunneling current for thinner oxides. At high corona stress fluences, gate oxide integrity defects control the magnitude of stress-induced leakage current measured at constan oxide field. It is suggested that the gate oxide integrity role is associated with the enhanced rate of the trap generation during stress. It is noted that the present findings employ a novel methodology for gate oxide integrity monitoring based on corona charging and contact potential difference measurement.

Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.


Nanomaterials ◽  
2021 ◽  
Vol 11 (7) ◽  
pp. 1803
Author(s):  
Zhen Zheng ◽  
Junyang An ◽  
Ruiling Gong ◽  
Yuheng Zeng ◽  
Jichun Ye ◽  
...  

In this work, we report the same trends for the contact potential difference measured by Kelvin probe force microscopy and the effective carrier lifetime on crystalline silicon (c-Si) wafers passivated by AlOx layers of different thicknesses and submitted to annealing under various conditions. The changes in contact potential difference values and in the effective carrier lifetimes of the wafers are discussed in view of structural changes of the c-Si/SiO2/AlOx interface thanks to high resolution transmission electron microscopy. Indeed, we observed the presence of a crystalline silicon oxide interfacial layer in as-deposited (200 °C) AlOx, and a phase transformation from crystalline to amorphous silicon oxide when they were annealed in vacuum at 300 °C.


2009 ◽  
Vol 20 (26) ◽  
pp. 264012 ◽  
Author(s):  
S A Burke ◽  
J M LeDue ◽  
Y Miyahara ◽  
J M Topple ◽  
S Fostner ◽  
...  

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