Comparison of Ultra-low-energy Ion Implantation of Boron and BF2

1999 ◽  
Vol 568 ◽  
Author(s):  
Jihwan Park ◽  
Hyunsang Hwang
Keyword(s):  
Sheet Resistance ◽  
Significant Loss ◽  
Oxide Semiconductor ◽  
Computationally Efficient ◽  
Enhanced Diffusion ◽  
Annealing Conditions ◽  
Ultrashallow Junctions ◽  
The Monte Carlo Method ◽  
Boron Implantation ◽  
Effect Transistor

ABSTRACTWe have compared the electrical characteristics and the depth profile of an ultrashallow junctions formed by boron implantation at 0.5 keV and BF2 implantation at 2.2 keV. The modeling of the boron profile was performed using the Monte Carlo method for an as-implanted profile and the computationally efficient method for transient-enhanced diffusion. A junction depth of BF2 is shallower than that of boron after annealing. HF dipping prior to rapid thermal annealing causes a significant loss of dopant and high sheet resistance. Considering the 0.1 νn metal-oxide-semiconductor field-effect-transistor (MOSFET) application, the optimizations of implantation and annealing conditions are necessary to satisfy the requirement ofjunction depth and sheet resistance.

Modeling of Damage Enhanced Diffusion of Implanted Boron in Silicon

1990 ◽  
Vol 201 ◽  
Author(s):  
V. C. Lo ◽  
S. P. Wong ◽  
Y. W. Lam
Keyword(s):  
High Dose ◽  
Boron Diffusion ◽  
Furnace Annealing ◽  
Enhanced Diffusion ◽  
Annealing Conditions ◽  
Boron Implantation ◽  
Dominant Point ◽  
Local Relaxation ◽  
And Diffusion ◽  
Defect Species

AbstractModeling of the damage enhanced diffusion (DED) behaviors of implanted boron in silicon of Powell’s experiment [1] has been performed. In his experiment, Powell showed that the diffusion of implanted boron in silicon was dependent on implantation dosage as well as on the annealing conditions. For low dose boron implantation, the extent of boron diffusion after 15 second RTP is less than that of furnace annealing at 900°C for 30 minutes. But the reverse is true for the high dose case, and a two-step annealing leads to least and minimal diffusion. In this work, implantation induced excess self-interstitials which generate mobile boron atoms at the intersititial sites are considered the dominant point defect species responsible for the DED. Both the local relaxation and diffusion of these excess self-interstitials are considered. The features of the DED reported by Powell are successfully reproduced and explained.

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

scholarly journals Challenges and Perspectives for Vertical GaN-on-Si Trench MOS Reliability: From Leakage Current Analysis to Gate Stack Optimization

Materials ◽  
2021 ◽  
Vol 14 (9) ◽  
pp. 2316
Author(s):  
Kalparupa Mukherjee ◽  
Carlo De Santi ◽  
Matteo Borga ◽  
Karen Geens ◽  
Shuzhen You ◽  
...  
Keyword(s):  
Field Effect Transistor ◽  
Dynamic Performance ◽  
Power Conversion ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Current Analysis ◽  
Power Transistors ◽  
Trench Structure ◽  
Effect Transistor ◽  
Gan On Si

The vertical Gallium Nitride-on-Silicon (GaN-on-Si) trench metal-oxide-semiconductor field effect transistor (MOSFET) is a promising architecture for the development of efficient GaN-based power transistors on foreign substrates for power conversion applications. This work presents an overview of recent case studies, to discuss the most relevant challenges related to the development of reliable vertical GaN-on-Si trench MOSFETs. The focus lies on strategies to identify and tackle the most relevant reliability issues. First, we describe leakage and doping considerations, which must be considered to design vertical GaN-on-Si stacks with high breakdown voltage. Next, we describe gate design techniques to improve breakdown performance, through variation of dielectric composition coupled with optimization of the trench structure. Finally, we describe how to identify and compare trapping effects with the help of pulsed techniques, combined with light-assisted de-trapping analyses, in order to assess the dynamic performance of the devices.

scholarly journals 4H-SiC Double Trench MOSFET with Split Heterojunction Gate for Improving Switching Characteristics

Materials ◽  
2021 ◽  
Vol 14 (13) ◽  
pp. 3554
Author(s):  
Jaeyeop Na ◽  
Jinhee Cheon ◽  
Kwangsoo Kim
Keyword(s):  
Dynamic Characteristics ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Switching Loss ◽  
Switching Speed ◽  
Polysilicon Gate ◽  
Effect Transistor ◽  
Switching Characteristics

In this paper, a novel 4H-SiC split heterojunction gate double trench metal-oxide-semiconductor field-effect transistor (SHG-DTMOS) is proposed to improve switching speed and loss. The device modifies the split gate double trench MOSFET (SG-DTMOS) by changing the N+ polysilicon split gate to the P+ polysilicon split gate. It has two separate P+ shielding regions under the gate to use the P+ split polysilicon gate as a heterojunction body diode and prevent reverse leakage `current. The static and most dynamic characteristics of the SHG-DTMOS are almost like those of the SG-DTMOS. However, the reverse recovery charge is improved by 65.83% and 73.45%, and the switching loss is improved by 54.84% and 44.98%, respectively, compared with the conventional double trench MOSFET (Con-DTMOS) and SG-DTMOS owing to the heterojunction.

Improving the accuracy of the charge-sheet model for the long-channel metal-oxide semiconductor field-effect transistor

1987 ◽  
Vol 65 (8) ◽  
pp. 995-998
Author(s):  
N. G. Tarr
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Inversion Layer ◽  
Potential Drop ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Analytic Approximation ◽  
Effect Transistor ◽  
Long Channel

It is shown that the accuracy of the charge-sheet model for the long-channel metal-oxide-semiconductor field-effect transistor can be improved by allowing for the small potential drop across the inversion layer, and by using a more accurate analytic approximation for the charge stored in the depletion region.

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