Scanning Probe Microscopy (SPM) for the Investigation of Local Electrical Properties of High-K Dielectric/Ferroelectric Films

1999 ◽  
Vol 567 ◽  
Author(s):  
S.A. Landau ◽  
P.-A. Weiß ◽  
N. Junghans ◽  
B.O. Kolbesen ◽  
D. Adderton ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Electrostatic Force ◽  
Local Area ◽  
Cmos Technology ◽  
Ferroelectric Materials ◽  
Lower Electrode ◽  
Force Microscopy ◽  
High K ◽  
High K Materials ◽  
High K Dielectric

ABSTRACTThin films of high-k dielectric/ferroelectric materials such as BaxSr1−xTiO3 (BST), PbZrxTi1−xO3 (PZT) and SrBi2Ta2O9 (SBT) are currently investigated for integration into high-density CMOS technology. Characterization of these materials by SPM techniques combines imaging of the morphology and microstructure of these films and recording of various electrical parameters at the same local area. Using commercial equipment we have investigated electrical properties such as polarization and leakage current behavior of MOD/MOCVD SBT by applying electrostatic force microscopy (EFM) and conducting atomic force microscopy (CAFM). After applying bias voltages of a few volts across the SBT films between the scanning tip and the lower electrode completely polarized/reverse polarized SBT layers could be observed by EFM. Even single crystallite polarization was imaged. However, unexpectedly some films showed incomplete polarization, which may be caused by local electrical field effects. Images taken by C-AFM displayed enhancement of leakage currents in grain boundary regions, in particular at depressions between adjacent crystallites. The results achieved demonstrate that SPM techniques operated in a variety of imaging and measuring modes, provide a tremendous potential in the elucidation of the microscopic properties of high-k materials.

On the Nature of Weak Spots in High-k Layers Submitted to Anneals

2004 ◽  
Vol 811 ◽  
Author(s):  
J. Pétry ◽  
W. Vandervorst ◽  
O. Richard ◽  
T. Conard ◽  
P. DeWolf ◽  
...  
Keyword(s):  
Atomic Force Microscopy ◽  
Strong Correlation ◽  
Positive Charge ◽  
The Other ◽  
Physical Analysis ◽  
Force Microscopy ◽  
Atomic Force ◽  
Other Hand ◽  
High K ◽  
High K Dielectric

ABSTRACTIn the path to the introduction of high-k dielectric into IC components, a large number of challenges have still to be solved. Some of the major issues concern the low mobility of carriers and the reliability of the devices. Trapped charges in the stack have been identified as being the cause of these issues. With this in mind, we used Conducting Atomic Force Microscopy, combined with physical analysis to understand the nature of these charges. In this contribution, we have studied the uniformity of thin HfO2 layers, with and without anneal. The Conducting Atomic Force microscopy measurements show spots of higher conductivity. Recording local IV's in those ‘weak’ spots suggests that they consist of positive charge. On the other hand, XPS and ToFSIMS analysis show a diffusion of the interfacial SiO2 upwards into the high-k layer. Finally, the comparison of samples with differing high-k material and crystallinity indicates a strong correlation between the weak spots and the presence of silicon in the film.

Wet Process Developments for Electrical Properties Improvement Of 3D MIM Capacitors

2007 ◽  
Vol 134 ◽  
pp. 379-382
Author(s):  
Claire Therese Richard ◽  
D. Benoit ◽  
S. Cremer ◽  
L. Dubost ◽  
B. Iteprat ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Copper Oxide ◽  
Leakage Current ◽  
Breakdown Voltage ◽  
3D Structure ◽  
Wet Process ◽  
High K ◽  
3D Architecture ◽  
High K Dielectric ◽  
Mim Capacitors

3D architecture is an alternative way to high-k dielectric to increase the capacitance of MIM structure. However, the top of this kind of structure is very sensitive to defectivity and then requires a special wet treatment. In this paper, we present the process flow for a 3D MIM integration in a CMOS copper back-end and a two steps wet process which provides very good electrical performances, i.e. leakage current lower than 10-9A.cm-2 at 5V / 125°C and breakdown voltage higher than 20V. At first, a SC1 step is done for electrode isolation improvement by material etching with good selectivity towards dielectric: that’s the electrode recess. In the second time, a HF step is done for copper oxide dilution and residues removal from the top of the 3D structure.

Laser annealed HfxZr1−xO2 high-k dielectric: Impact on morphology, microstructure, and electrical properties

2008 ◽  
Vol 92 (11) ◽  
pp. 113501 ◽  
Author(s):  
Dina H. Triyoso ◽  
Greg Spencer ◽  
Rama I. Hegde ◽  
Rich Gregory ◽  
Xiang-Dong Wang
Keyword(s):  
Electrical Properties ◽  
High K ◽  
High K Dielectric

Wafer Level Statistical Evaluation of the Proton Radiation Hardness of a High-k Dielectric/Metal Gate 45 nm Bulk CMOS Technology

2013 ◽  
Vol 50 (5) ◽  
pp. 213-222
Author(s):  
C. Claeys ◽  
S. Iacovo ◽  
D. Kobayashi ◽  
A. Mercha ◽  
A. Griffoni ◽  
...  
Keyword(s):  
Statistical Evaluation ◽  
Cmos Technology ◽  
Radiation Hardness ◽  
Proton Radiation ◽  
Wafer Level ◽  
Metal Gate ◽  
High K ◽  
High K Dielectric

The Influence of Defects and Impurities on Electrical Properties of High-k Dielectrics

2008 ◽  
Vol 608 ◽  
pp. 55-109 ◽  
Author(s):  
Jaroslaw Dąbrowski ◽  
Seiichi Miyazaki ◽  
S. Inumiya ◽  
G. Kozłowski ◽  
G. Lippert ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Carrier Transport ◽  
Dielectric Material ◽  
Electrical Breakdown ◽  
Charge Trapping ◽  
Basic Knowledge ◽  
Dielectric Films ◽  
Low Leakage ◽  
High K ◽  
High K Dielectric

Electrical properties of thin high-k dielectric films are influenced (or even governed) by the presence of macroscopic, microscopic and atomic-size defects. For most applications, a structurally perfect dielectric material with moderate parameters would have sufficiently low leakage and sufficiently long lifetime. But defects open new paths for carrier transport, increasing the currents by orders of magnitude, causing instabilities due to charge trapping, and promoting the formation of defects responsible for electrical breakdown events and for the failure of the film. We discuss how currents flow across the gate stack and how damage is created in the material. We also illustrate the contemporary basic knowledge on hazardous defects (including certain impurities) in high-k dielectrics using the example of a family of materials based on Pr oxides. As an example of the influence of stoichiometry on the electrical pa-rameters of the dielectric, we analyze the effect of nitrogen incorporation into ultrathin Hf silicate films.

scholarly journals Laser Ablation Ceramic Target for 8YSZ High-k Dielectric Electrolyte thin Films Precessed by PLD on Si(100) and Pt/Si(111)

2020 ◽  
Vol 71 (7) ◽  
pp. 272-277
Author(s):  
Rovena Veronica Pascu
Keyword(s):  
Thin Films ◽  
X Ray Diffraction ◽  
Stabilized Zirconia ◽  
X Ray ◽  
Force Microscopy ◽  
Atomic Force ◽  
High K ◽  
Potential Applications ◽  
Electrochemical Devices ◽  
High K Dielectric

The cubic structure 8YSZ (8%Yttria-Stabilized Zirconia) thin films deposited by PLD(Pulsed Laser Deposition) on substrates Si (100) and Pt/Si (111) by identical control parameters have potential applications as electrolytes for planar micro electrochemical devices like Lambda oxygen sensors and IT-�SOFC. It appearance differences in polycrystalline structural and optical characterization by XRD (X-ray Diffraction), SEM (Scanning Electron Microscope), AFM (Atomic Force Microscopy) and V- VASE (Variable Angle Spectroscopic Ellipsometry. The differences are relating on crystalline dimensions, lattice parameters; surface roughness measured by V- VASE and AFM are presented synthetic to evidence the differences generated by substrates.

Application of high-k dielectric stacks charge trapping for CMOS technology

2010 ◽  
Vol 166 (2) ◽  
pp. 170-173 ◽  
Author(s):  
Satinder K. Sharma ◽  
B. Prasad ◽  
Dinesh Kumar
Keyword(s):  
Charge Trapping ◽  
Cmos Technology ◽  
High K ◽  
High K Dielectric
Sign in / Sign up

Export Citation Format

Share Document